Advanced Micro Devices Corporation

Ati Technologies Ulc

Globalfoundries Inc.

S3 Incorporated, Inc.

Francisco Leonel Duran

Alexander J Branover

Anthony Asaro

Vilas K Sridharan

Joseph Lee Greathouse

Alan Dodson Smith

Felix Kuehling

Philip Ng

Vydhyanathan Kalyanasundharam

Maurice B Steinman

Paul Blinzer

David Francis Tobias

Andrew William Lueck

Walter G Fry

Nippon Harshadk Raval

Ming L So

Ali Ibrahim

Hanbing Liu

Krishna Sai Bernucho

Gary H Simpson

Seng-Khoon Tng

Noah Beck

Mom-Eng Ng

Dan P Shimizu

Laura M Smith

W Paul Montgomery

Xiaogang Zheng

Winston Tsai

John D Wilkes, Jr

Mahesh UdayKumar Wagh

Carlos Vallin

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Dynamic repartition of memory physical address mapping

An exemplary computing device comprises an in-band processor and an out-of-band controller. The exemplary computing device also comprises a machine check architecture that includes a pipeline and a plurality of error detectors. The error detectors are configured to detect errors that occur in a plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline. Various other devices, systems, and methods are also disclosed.

Devices, systems, and methods for out-of-band logging and delivery of error reports

An exemplary system comprises a cluster of nodes that are communicatively coupled to one another via at least one direct link and collectively include a plurality of memory devices. The exemplary system also comprises at least one system memory manager communicatively coupled to the cluster of nodes. In one example, the system memory manager is configured to allocate a plurality of sharable memory pools across the memory devices. Various other systems, methods, and computer-readable media are also disclosed.

Systems and methods for sharing memory across clusters of directly connected nodes

An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.

Devices, systems, and methods for injecting fabricated errors into machine check architectures

A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.

Steering tag support in virtualized environments

Processor power may be managed by executing state storage and power gating instructions after receiving an idle indication. The idle indication may be received while the processor is executing instructions in a first mode, and the processor may execute the state storage and power gating instructions in a second mode. The state storage and power gating instructions may be inaccessible to the processor when operating in the first mode.

Power management through power gating portions of an idle processor

A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Method and apparatus for transitioning a system to an active disconnect state

A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.

System and method for limiting processor performance

A technique for rebalancing performance levels of one or more add-in cards is presented. Rebalancing occurs whenever a hot-plug event occurs and a change in status of a mismatch condition occurs. For example, if an add-in card is inserted that is unable to operate at the current performance level, rebalancing of the performance level occurs. Thus, for an insertion event, the performance level of all cards may be lowered. Alternatively, if an add-in card is removed and a mismatch is resolved, rebalancing of the performance level occurs. Thus, for a removal event, the performance level may be increased. The rebalancing includes disabling any enabled cards and enabling all cards at a different performance level. In one embodiment, the cards are sorted according to highest performance level available and enabled in an order of lowest to highest of the highest performance level available.

Automatic bus speed and mode balancing after hot-plug events on hot-plug driver

An analog joystick interface system for overcoming the deficiencies of the conventional analog joystick interface by supporting positional tracking in both a legacy and an enhanced mode. In the legacy mode, the host calculates the relative physical orientation of a positional grip of an analog joystick by relying upon continuous polling techniques. In the enhanced mode, a watch dog timer relieves the host of the need to continuously poll by directly providing the host with positional data concerning the relative physical orientation of the positional grip. The ability of the joystick interface to provide both the legacy and enhanced modes ensures that compability issues concerning the legacy DOS-based software applications and CPU allocation problems associated with continuous polling are resolved without considerably increasing cost or complexity of the joystick interface.

Multiple mode analog joystick interface

Growing community of inventors

Austin, TX, United States of America

Francisco Leonel Duran