Texas Instruments Corporation

Francisco A Cano

Erkan Bilhan

Juan C Martinez

Nagaraj Narasimh Savithri

Anthony Martin Hill

Clive D Bittlestone

Devanathan Varadarajan

David A Thomas

Luat Q Pham

Arvind Kumar

Jose Luis Flores

Kalpesh Amrutlal Shah

Duane J Young

Vijaya Gunturi

Robert E Farrell

Deepak Kapoor

Rajib Nag

Haldun Haznedar

A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

Stress reduction on stacked transistor circuits

An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

Adaptive voltage scaling using temperature and performance sensors

A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

Screening of memory circuits

Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Circuits and methods for asymmetric aging prevention

A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.

Compensatory memory system

An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

Semiconductor device testing

An integrated circuit has a power grid formed from a first set of power buses and on a metal interconnect level M a second set of power buses and on interconnect level M and a third set of power buses and on interconnect level M The set of power buses on level M are oriented in the same direction as the set of power buses on level M and both sets of buses are located coincidentally. A high power logic cell is pre-defined with a set of M -M power vias and so that logic cell can be positioned in a horizontal row unconstrained by pre-positioned M -M power vias. Dummy cell with M -M power vias is positioned as needed so as not to exceed a maximum strapping distance D A maximum value for distance D is selected based on dynamic power requirements of nearby logic cells as determined by simulation. A method for designing and fabricating integrated circuit is described.

Method for power routing and distribution in an integrated circuit with multiple interconnect layers

A clock generation circuit with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry in or out of the non-overlap feedback path on signal line . A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit or a scan latch also can select the non-overlap time period.

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Missouri City, TX, United States of America

Francisco A Cano