Digital Equipment Corporation

Vlsi Technology, Inc.

Francisca Tung

James C Lee

Arshad Ahmad

Myrna E Castro

Thomas Joel Massingill

Richard L Beck

Chune Lee

Tsing-Chow Wang

Marlita F Macaraeg

Serena M Luo

Victor H Okumoto

The ball bump structure of the subject invention provides a hermetically sealed bond pad at the surface of a semiconductor chip. An adhesion pad is formed at the surface of the bond pad. The adhesion pad includes a barrier layer, preferably a titanium/tungsten alloy, and a bonding layer, for example, a sputtered gold layer. A gold ball bump is formed on the adhesion pad. Methods for forming the improved structure herein are also disclosed.

Bump formation on yielded semiconductor dies

A method of forming a multilayer circuit board is disclosed which includes a build-up process in which, beginning with a solidified layer of the dielectric disposed upon a substrate, alternate layers of conducting metal and dielectric are sequentially deposited. Each layer of conducting metal lines is defined using photoresist and a photolithographic technique. After the lines are deposited, the photoresist is removed and a second layer of photoresist defines the conductive posts which function as through holes between metal layers. After each layer of conductive line and posts is formed, and the photoresist is removed, the dielectric is flowed into place and solidified to insulate adjacent metal lines and posts. The process may be repeated as many times as necessary to build up layers of conducting metal and dielectric, and form the completed multilayer wiring board.

Sequential multilayer process for using fluorinated hydrocarbons as a

A method of forming conductive bumps on the bond pads of one or more ICs is described wherein a barrier metal layer such as TiW is first formed over the bond pads in order to passivate the surface of the one or more ICs, an electroplatable base comprising an adhesion metal layer is then formed over each of the bond pads by using a contact metal mask to screen off other portions of the IC surfaces, and a conductive bump is then formed on top of the electroplatable base by either electroplating or electroless bath techniques. A structure for holding a plurality of good IC dies while conductive bumps are being electroplated on their bond pads is also described.

Structure for holding integrated circuit dies to be electroplated

A very fine line three-dimensional package is constructed without lamination during construction of the signal core. Construction of the signal core employs a method of line and hole formation and planarization without drilling, and avoids imposing excessive stress on the package during its assembly. In forming the three-dimensional structure, a power core which may comprise a single or multiple layers is manufactured in the conventional method using a very high dielectric constant material. A signal core is on both sides of the power core, using a sequential approach with a low dielectric constant material. The method comprises utilizing photoresist techniques to define the regions of horizontal lines running parallel to the surface of the power core substrate and vertical posts running perpendicular to the surface of the power core, as each layer of lines and posts is established. After metallization of the lines and posts, the dielectric is flowed over the pattern of lines and posts to form a finished layer of the signal core. The sequence is repeated as many times as necessary to build up the required wiring pattern in the signal core. Layers of signal core are built up sequentially on both sides of the power core by alternating between depositing conducting metal and flowing and solidifying a dielectric in place.

Double-sided hybrid high density circuit board and method of making same

A multiple chip interconnection system and package for interconnecting and cooling integrated circuits includes an electrically-conductive plate 10 having an upper surface 12. On the upper surface 12, a first layer of polyimide 16 or other electrically-insulating material is deposited. One or more layers of electrical interconnections 17, 18, 21, 22, and insulating material 19, 24, are then disposed on the insulating material 16 to provide a network of electrical connections embedded in insulating material, yet which is sufficiently thin to offer minimal thermal resistance to the transfer of heat from integrated circuits mounted thereon to the plate 10. After the layers of interconnections are completed, one or more conductive planes are deposited across the interconnections to serve as a mounting surface for the integrated circuits and to distribute power and ground signals as necessary. One or more integrated circuits 40 are then attached to the plane 32 and suitable interconnections made between the integrated circuits and desired regions 34 of the plane. The package is completed by attaching an air- or water-cooled heat sink 54 to the opposite side of plate 10 from the integrated circuits. The integrated circuits may be protected by a lid 50, 52, and pins attached to openings in the plate 10 to connect the module to a printed circuit board or other desired connector.

Growing community of inventors

Los Gatos, CA, United States of America

Francisca Tung