Nxp B.v.

Francis Zaato

Theodore James Letavic

Wibo Daniel Van Noort

Wibo Van Noort

Charudatta Mandhare

An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Integrated circuit with trimming

A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.

Growing community of inventors

Fishkill, NY, United States of America

Francis Zaato