Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

National University of Singapore

United Test and Assembly Test Center Ltd.

Francis YongWee Poh

Juan Boon Tan

Danny Pak-Chum Shum

Yi Jiang

Tze Ho Simon Chan

Yang Hong

Shyue Seng Tan

Alex See

Wanbing Yi

Guowei Zhang

Fan Zhang

Hien Boon Tan

Ganesh S Samudra

Jingsheng Chen

Daxiang Wang

James Yongmeng Lee

Pengfei Guo

Danny PakChum Shum

Rodel Manalac

Sneedharan Pillai Sneelal

C K Lau

Shifeng Zhao

Jaime Siat

Roland Cordero

Shaohai Chen

Magnetic tunnel junction (MTJ) structures, spin transfer torque magnetic random access memory (STT MRAM) structures, and methods for fabricating integrated circuits including such structures are provided. In an embodiment, an MTJ structure includes a cobalt iron carbon (CoFeC) fixed reference layer. Further, the MTJ structure includes a cobalt iron carbon (CoFeC) free storage layer. Also, the MTJ structure includes a tunnel barrier layer between the fixed reference layer and the free storage layer.

MTJ structures, STT MRAM structures, and methods for fabricating integrated circuits including the same

Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

Integrated magnetic random access memory with logic device

Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate. A floating gate is disposed over a transistor well. A control gate disposed over a control well is coupled to the floating gate. The control gate includes a control capacitor. A non-self-aligned source/drain (S/D) region is disposed within the transistor well and serves as an erase terminal.

Simple and cost-free MTP structure

A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

Disclosed herein are memory cell arrays, semiconductor devices, and methods for fabricating semiconductor devices. In one embodiment, a memory cell array includes first, second, third, and fourth memory cells each having a first transistor and a second transistor. First and second word-lines are coupled with the gates of the first transistors of the first and second memory cells. The second and a third word-line are coupled with the gates of the second transistors of the third and fourth memory cells.

Non-volatile memory cell arrays and methods of fabricating semiconductor devices

An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.

Integrated circuit package with leadframe enhancement and method of manufacturing the same

A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.

Process flow for a performance enhanced MOSFET with self-aligned, recessed channel

Growing community of inventors

Singapore, Singapore

Francis YongWee Poh