International Business Machines Corporation

Francis Woytowich

Pamela Sue Gillis

Chandramouli Visweswariah

Jinjun Xiong

Donald Lawrence Wheater

Tad Jeffrey Wilder

Jack Robert Smith

Leendert M Huisman

Glen E Richard

Leah M Pastel

Thomas Webster Bartenstein

Raymond J Rosner

Tian Xia

Ronald J Prilik

Douglas C Heaberlin

L Owen Farnsworth

Kevin William McCauley

Edward E Horton, Iii

Jose M Martinez

In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.

Method and apparatus for selecting voltage and frequency levels for use in at-speed testing

The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

Method and apparatus for increased effectiveness of delay and transition fault testing

A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Internal cache for on chip test data storage

A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

Self-timed AC CIO wrap method and apparatus

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Charlotte, VT, United States of America

Francis Woytowich