Rockwell International Corporation

Francis M Erdmann

Moiz M Beguwala

Addison B Jones

Frederick Vescial

Frederick Aronowitz

Thomas M Wirt

Kenneth L Steele

William T Schmars

An alignment and path length control apparatus having a mirror housing having a base and a closed wall. The base has a mirrored external surface. The closed wall has a central axis. The closed wall is joined to the base at a base end of the closed wall by a flexible web. The closed wall extends above the base and terminates at a rim defining an aperture. The base has a central region coupled to the cylindrical wall. A post extends from the central region of the base within the cylindrical wall to a top end. A mirror axis extends from the mirrored external surface through the post. The central axis is substantially parallel to the mirror axis. An alignment transducer responds to a first alignment control signal by applying at least a first force between the post and the wall to deflect the mirror axis with respect to the central axis. A linear transducer responds to a linear displacement control signal by applying an axial force to the post to displace the central region longitudinally along the central axis.

Interferometer alignment control apparatus

A method of forming a superconductor-barrier-superconductor junction device by the steps of depositing a first superconductive layer on a substrate, forming a barrier layer on the first superconductive layer and depositing a second superconductive layer on the barrier layer. A layer of photoresist is then deposited over the second superconductive layer and patterned together with the second superconductive layer to form a mesa structure. A dielectric layer is deposited over the mesa structure, and the photoresist layer portion is dissolved thereby lifting off the dielectric portion overlying said second superconductive layer portion.

Process for in-situ formation of niobium-insulator-niobium Josephson

There is shown and described a memory array using MNOS/MOS transistors. The memory devices are nonvolatile, metal-nitride-oxide-semiconductor (MNOS) variable threshold voltage transistors and the metal-oxide semiconductor (MOS) input-output devices exhibit fixed threshold voltages. The MOS devices are fabricated first and the MNOS memory devices are fabricated thereafter. This memory gate last (MGL) arrangement eliminates the need for high temperature process steps after the formation of the MNOS device gate dielectric in the array devices. This operation results in an MNOS/MOS memory array which exhibits excellent ionizing radiation hardness characteristics as well as memory properties which are improved over present radiation hardened MNOS/MOS arrays.

Fabrication of a nonvolatile memory array device

A process for the direct thermal nitridation of silicon semiconductor devices in which the semiconductor body is placed in an atmosphere of N.sub.2, at a temperature of less than 1000.degree. C. The N.sub.2 is activated by an RF electrical field which ionizes the nitrogen, which then combines with the silicon surface.

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Anaheim, CA, United States of America

Francis M Erdmann