International Business Machines Corporation

Francis M Bonevento

Ernest Nelson Mandese

Richard N Mendelson

Andrew B McNeill

Dhruvkumar M Desai

Sammy D Dodds

Chester A Heath

Douglas R Chisholm

Joseph P McGovern

Eugene M Thomas

Douglas R Chrisholm

A microprocessor system includes a processor unit, one or more subsystem adapter units, optional I/O devices which may attach to the adapters, and a bus interface. Memory in the processor and memory in the adapters are used by the system as a shared memory which is configured as a distributed First In First Out (FIFO) circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing self-describing control elements on the pipe which represent requests, replies, and status information. The units send and receive self-describing control elements independent of the other units which allows free flowing asynchronous delivery of control information and data between units. The distributed, shares memory can be organized as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements and the other pipe for inbound control elements. The control elements have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

System for asynchronously delivering self-describing control elements

This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus. An interrupt controller is coupled to the microprocessor and bus for recognizing delivery of an interrupt signal and for periodically generating an interrupt reset signal and delivering reset signals to all of the input/output devices simultaneously for setting all of the devices to a condition indicative of no request for access to said microprocessor.

Personal computer system with interrupt controller

A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command. The host processor reads the DIIP to determine which logical devices have at least one logical interrupt pending for an indirect command. A plurality of logical interrupts for a single logical device may be cleared with a single reset interrupt command from the host processor.

Interrupt handling for a computing system with logical devices and

A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Command delivery for a computing system for transferring data between a

A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

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Boca Raton, FL, United States of America

Francis M Bonevento