Taiwan Semiconductor Manufacturing Comp. Ltd.

Lam Research Corporation

Francis Ko

Jean Wang

Henry Lo

Chih-Wei Lai

Chun-Hsien Lin

Chen-Hua Douglas Yu

Kewei Zuo

Ping-Hsu Chen

Amy Wang

Chi-Chun Hsieh

Charlie Lee

Sandy Chen

Shin-Puu Jeng

Wen-Chih Chiou

Shang-Yun Hou

Yi-Li Hsiao

Sunny Wu

Tzu-Yu Wang

Lawrance Sheu

Chuan-Kai Lo

Richard Chen

Lawrence Chen

Chang-Tai Chiao

Young Tong Tsai

Chun-Hsien Lim

A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

Clustering for prediction models in process control and for optimal dispatching

A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Forming interconnect structures using pre-ink-printed sheets

A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.

Automatic virtual metrology for semiconductor wafer result prediction

Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.

Near non-adaptive virtual metrology and chamber control

A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of metrological data for at least one layer of the semiconductor substrate may be estimated, and an optimum CMP process recipe may be selected based on the set of metrological data. The optimum CMP process recipe may be implemented on the semiconductor substrate.

Method and system for controlling copper chemical mechanical polish uniformity

A method to enable wafer result prediction from a batch processing tool, includes collecting manufacturing data from a batch of wafers processed in batch in the batch processing tool, to form a batch processing result; defining a degree of freedom of the batch processing result based on the manufacturing data; and performing an optimal curve fitting by trial and error for an optimal function model of the batch processing result based on the batch processing result.

Methodology to enable wafer result prediction of semiconductor wafer batch processing equipment

A system, method, and computer readable medium for extracting a key process parameter correlative to a selected device parameter are provided. In an embodiment, the key process parameter is determined using a gene map analysis. The gene map analysis includes grouping highly correlative process parameter and determining the correlation of a group to the selected device parameter. In an embodiment, the groups having greatest correlation to the selected device parameter are displayed in a correlation matrix and/or a gene map.

System for extraction of key process parameters from fault detection classification to enable wafer prediction

A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.

System and method for enhanced control of copper trench sheet resistance uniformity

A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.

Auto routing for optimal uniformity control

A semiconductor processing method includes processing a first substrate while detecting at least one first processing parameter value in a first apparatus. The first processing parameter is analyzed, thereby yielding at least one first predicted parameter value. The first predicted parameter value is compared with a first pre-defined parameter value, thereby yielding at least one first comparison result. A first recipe is applied corresponding to the first comparison result for processing a second substrate in the first apparatus.

Method and system for yield and productivity improvements in semiconductor processing

A method of monitoring uniformity of a wafer is provided. A wafer parameter is selected. Manufacturing data is collected. The manufacturing data includes measurements of the selected wafer parameter. An average offset profile of the wafer parameter for a first and second wafer is determined using the manufacturing data. The first and second wafer are associated with a product type and were processed by a processing tool. An offset profile for a third wafer is predicted for a wafer using the average offset profile. The third wafer is associated with the product type and was processed by the processing tool.

Prediction of uniformity of a wafer

A method for increasing etching selectivity of a developed silicon-containing photoresist layer on a non-silicon containing photoresist layer on a substrate. The developed silicon-containing photoresist layer includes polymer chains containing silicon. Next, the developed silicon-containing photoresist layer and uncovered portions of the non-silicon containing photoresist layer are exposed to an ultraviolet (UV) light, where the UV light emanates from a UV generating agent, such as neon, xenon, helium, hydrogen, or krypton gas in an inert gas (e.g., argon, etc.) plasma. A top portion of the developed silicon-containing photoresist layer is then converted to a hardened layer, where the hardened layer is created by cross-linking the polymer chains containing silicon and the cross-linking is activated by the UV light. Next, an etch is performed on the uncovered portions of the non-silicon containing photoresist layer and the substrate using the hardened layer.

Method for argon plasma induced ultraviolet light curing step for increasing silicon-containing photoresist selectivity

A method for monitoring a processing tool in a semiconductor manufacturing facility includes selecting key hardware parameters for a virtual sensor system based on manufacturing data associated with a fabrication tool and collecting manufacturing data associated with the fabrication tool. The method further includes dynamically maintaining the virtual sensor system during the manufacture of a plurality of semiconductor products and using the virtual sensor system and the collected manufacturing data for predicting a condition of a semiconductor product after being processed by the fabrication tool.

Method and apparatus to enable accurate wafer prediction

Provided is a method for increasing an etching selectivity of photoresist material. The method initiates with providing a substrate with a developed photoresist layer. The developed photoresist layer on the substrate is formulated to contain a hardening agent. Next, the substrate is exposed to a gas, where the gas is formulated to interact with the hardening agent. A portion of the developed photoresist layer is then converted to a hardened layer where the hardened layer is created by an interaction of the hardening agent with the gas. Some notable advantages of the discussed methods of increasing the selectivity of a photoresist include improved etch profile control. Additionally, by combining fabrication steps such as the hardening of the photoresist in an etch chamber, downstream etching processes may be performed without having to transfer the wafer to an additional chamber, thereby improving wafer throughput while minimizing handling.

Plasma enhanced method for increasing silicon-containing photoresist selectivity

The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

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Taichung, Taiwan

Francis Ko