Broadbus Technologies, Inc.

Mueller International, LLC

Arris Enterprises LLC

Francis J Stifter, Jr

Michael A Kahn

Ian Phillip Harvey

Szabolcs Zigovszki

Matthew Sargeant

Catherine A Yadlon

Matt Allen Thomas

Jason P Colangelo

Technologies are described herein for activating one or more operating modes of a register in a meter. The register is operated in a first mode. Light detections indicating whether the register is exposed to light or isolated from light are read. It is determined whether a condition is met based on the light detections. Upon determining that the condition is met, operating the register in a second mode.

Mode activation using light detection

Technologies are described herein for compensating for inaccuracies in flow measurement in real-time during accumulation of usage. A pulse count indicating an amount of flow in a meter over a measurement period is read. An average flow rate through the meter for the measurement period is determined and a correction factor is looked up from a table based on the average flow rate. A total usage accumulator for the meter is then updated with the amount of flow over the measurement period based on the pulse count and the correction factor.

Real-time flow compensation in usage accumulation

In lieu of merely forwarding different selected content including originally received decoder information (e.g., timing information) to a respective user for a newly selected data stream, a server modifies decoder information of a newly transmitted data stream in accordance with a previously transmitted stream (or a master clock associated with the user) such that respective decoder state information used to decode a first stream of content can also be used to decode a second stream of content. That is, the server encodes and transmits newly selected content to a requestor in accordance with current decoder state information already used by the requestor to decode previously received content. This enables splicing of content together from two or more asynchronous data streams into a single, contiguous data stream even though the data streams originate with different sets of timing information.

Content distribution and switching amongst data streams

A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Data access and multi-chip controller

A system includes multiple input ports that forward received data (e.g., data packets) to each of multiple queues. Data received at the input ports of the system can be somewhat random or 'bursty' at times. That is, the input ports can receive data at a variable bit rate or unspecified bit rate from an internal system source or an external source such as an FTP (File Transfer Protocol) server or SCSI disk array. The queues output data at a constant bit rate. A two-dimensional scheduler associated with the system forces random inbound server traffic from the input ports to adhere to a QoS (Quality of Service) agreement such that the random nature of the inbound traffic does not negatively affect the deterministic guarantees of existing server traffic output from the queues. In other words, techniques herein ensure adherence to QoS requirements among the data flows, without overflowing the queues.

Methods and system to manage data traffic

An on-demand server system herein includes a memory controller that coordinates access to one or more flash-based memory devices. The flash devices store large amounts of video content that can be selectively viewed on-demand by each of multiple destinations over a respective network. In addition to having access to an array of flash memory devices, the memory controller has access to a corresponding read buffer and write buffer. Use of the read buffer and the write buffer enable the memory controller to switch between transferring data stored in the write buffer to the array of memory devices and transferring the data in the array of memory devices to the read buffer. The write buffer stores on-demand video content that can be selected for viewing by different users. The read buffer stores segments of the on-demand video content currently streamed to the users.

Growing community of inventors

Hampton Falls, NH, United States of America

Francis J Stifter, Jr