Infineon Technologies Richmond, LP

Infineon Technologes Richmond, LP

Francis Goodwin

Michael Rennie

Jonathan Philip Davis

A pattern can be projected on a resist film layer deposited on a semiconductor surface. The pattern can include structural elements having different feature sizes. Structural elements having feature sizes below a certain limit are not resolved on the resist film layer. The dimension of the corresponding resist pattern can be reduced and the difference can be related to focus parameters of the exposure tool.

Method and arrangement for controlling focus parameters of an exposure tool

A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, sources and drains of various devices. In a one example, the wafer is coated with a planarizing anti-reflective coating (ARC), which then supports imaging of gate contacts using a positive DUV or MUV resist. This processing allows the nitride cap of certain transistor gates to be replaced with an oxide. In this example, the ARC can serve as an etch guide for selective removal of a film.

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Delmar, NY, United States of America

Francis Goodwin