International Business Machines Corporation

Siemens Aktiengesellschaft

Francis E Froebel

Jens G Pohl

Eric Jeffrey White

Ronald R Uttecht

Stephen G Starr

Albert J Gregoritsch, Jr

Sheldon C Rieley

Harold W Conru

David Lewis Gardell

Mohammed S Shaikh

Gary H Irish

The present invention provides a method for forming an improved lead-on chip semiconductor module and an improved module of this type. In a lead-on chip semiconductor device, a semiconductor chip which has a major surface having input and output bonding pads thereon, is secured to a lead frame having a plurality of leads adjacent the bonding pads by means of bonding wires connecting a respective one of the leads to a pad on the chip. A coating of dielectric material having a Young's modulus in the range of about 10 psi to about 500 psi is disposed around the entire length of each of the wires and over the pads and over the portion of the respective leads to which the wires are connected to act as a stress buffer. This material preferably has a T.sub.g of at least as low as -40.degree. C. Also preferably this package is encapsulated with conventional encapsulant.

Encapsulated semiconductor chip module and method of forming the same

A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.

Personalized area leadframe coining or half etching for reduced

A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

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Essex Junction, VT, United States of America

Francis E Froebel