Micron Technology Incorporated

Francis Chew

Bruce A Liikanen

Gerald L Cadloni

Larry Joseph Koudele

Michael Sheperek

A memory profiling system can generate profiles for target memory units of a memory component during runtime of the memory component. The memory profiling system can identify target memory units based on trigger conditions such as memory units crossing a specified depth in error recovery, receipt of a vendor specific (VS) command, memory unit retirement, or excessive background scan rates. In some cases, the memory profiling system can identify additional target memory units that are related to identified target memory units. The characterization processes can include computing voltage threshold (vt) distributions, Auto Read Calibration (ARC) analysis, Continuous Read Level Calibration (cRLC) analysis, DiffEC metrics, or gathering memory component metrics. The memory profiling system can store the generated profiles and can utilize the generated profiles to adjust operating parameters of one or more memory elements of the memory device, in real time.

Memory element profiling and operational adjustments

The rate at which reads on a target memory portion initiate error recovery procedures can be monitored in real-time. Trigger rates can be used to perform analysis of a memory sub-system or to implement improvements in the memory sub-system. Trigger rate monitoring can include accessing a count of error recovery initializations for a target memory portion, wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-stage error recovery process was performed. Trigger rate monitoring can further include accessing a count of read operations corresponding to the target memory portion. The count of error recovery initializations and the count of read operations can be used to compute a trigger rate. The trigger rate, or multiple trigger rates from various times or from various target memory portions, can be used to compute a metric for the memory portion(s).

Real time trigger rate monitoring in a memory sub-system

Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Dynamic background scan optimization in a memory sub-system

A memory system is disclosed, including a memory component and a processing device configured to decode one or more codewords saved to a memory region of the memory component, detect that a number of bit errors corresponding to the decoding of the codeword exceeds a correction capability of the processing device, and execute an error recovery routine to reduce the number of detected bit errors to within the correction capability. The error recovery routine can include error recovery operations that are sequentially executed either until the number of bit errors is successfully reduced to within the correction capability or until a set of the error recovery operations has been executed. The error recovery operations can be ordered according to one or more factors, including energy used to execute a respective error recovery operation, a duration of the respective operation, and/or a likelihood of success of the respective operation.

Memory components with ordered sweep error recovery

Several embodiments of memory devices and systems for real time block failure analysis are disclosed herein. In one embodiment, a system includes a memory array including a plurality of memory cells and a processing device coupled to the memory array. The processing device is configured to sense, in response to detection of an error associated with a subset of a plurality of memory cells of the memory device, a state associated with each memory cell of the subset of the plurality of memory cells. The processing device is further configured to store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset.

Real time block failure analysis for a memory sub-system

A memory system can identify target memory units to characterize by generating Cumulative Distribution Function (CDF)-based data for each memory unit and analyzing the CDF-based data to identify target memory units that are exceptional. Such target memory units can be those with CDF-based data with extrinsic tails or that crosses an info limit threshold. The memory system can perform characterization processes for the target memory units, e.g. using an Auto Read Calibration (ARC) analysis or a Continuous Read Level Calibration (cRLC) analysis. A manufacturing process for the memory device can use results of the characterization processes, e.g. by mapping them to types of problems observed during testing. Alternatively, results of the characterization processes to can be used during operation of the memory device, e.g. to adjust the initial read voltage threshold, the read retry voltage values, or the order of read retry voltages used in data recovery.

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Boulder, CO, United States of America

Francis Chew