International Business Machines Corporation

Francis Bredin

Bertrand Gabillard

Thierry Cantiant

Gerard Boudon

Pierre Coppens

Bertrand Boulet

Francois Auguste Roger Meunier

Claude Sitbon

Philippe Desbarbieux

Jean-Michel Proust

A method and system for monitoring speed of a vehicle moving along a road that includes risk zones. The method determines: road conditions for each risk zone; a threshold speed of each risk zone based on the road conditions and on a distance to a posted speed limit within a high risk zone; a geographical position of the vehicle, a current risk zone in which the vehicle is moving based on the stored geographical position of the vehicle; and a current speed of the vehicle moving in the current risk zone which exceeds the threshold speed of a particular risk zone, resulting in performing a subsequent action (triggering an alarm within the vehicle, presenting a message to a driver in the vehicle, and/or automatically regulating the speed of the vehicle). The action is specific to the particular risk zone and dependent on the road conditions.

Method and system for monitoring speed of a vehicle

A computer implemented method for automatically identifying one or more metrics for performing a CMMI evaluation of an entity, wherein the CMMI evaluation is performed at a particular CMMI level and the method comprises the steps of accessing an electronic database of a plurality of candidate metrics, providing a first list of requirement elements to define a set of specific requirements of the entity, providing a second list of requirement elements to define a set of general requirements of the business field of the entity, searching for a first subset of metrics from the plurality of candidate metrics that match the first list and second list of requirement elements, searching for a second subset of metrics from the first subset of metrics that match with the CMMI level, and outputting the second set of metrics in a user-friendly format suitable for the CMMI evaluation.

System and method for automatically selecting one or more metrics for performing a capacity maturity model integration

A system and method for controlling the unintended rolling of a rolling stock, the rolling stock having a driver park brake, and an in-vehicle network for signals transmission, the method comprises the steps of selecting among the signals transmitted over the in-vehicle network, a set of predefined signals, then analyzing the status of the selected signals to determine a regulation process to be applied to the rolling stock, and monitoring the regulation process.

System and method for monitoring parking brake release

A non-integer fractional divider is disclosed. According to the present invention, the non-integer fractional divider comprises means for dividing a reference clock signal having a period 'P' by a non-integer ratio 'K'. In a preferred embodiment, the divider comprises means for receiving a plurality &lsquo;N&rsquo; of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a &lsquo;P/N&rsquo; delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality &lsquo;N&rsquo; of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio &lsquo;K&rsquo;. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the non-integer part of the non-integer ratio. Then, dividing means are coupled to the combining means for dividing the shifted clock signal by the integer part of the non-integer ratio.

Programmable non-integer fractional divider

A non-integer fractional divider divides a reference clock signal having period P by a non-integer ratio K. The divider includes multiplexers to receive a plurality N of clock signals wherein each clock signal is equally phase shifted by a P/N delay. Incrementers coupled to the multiplexers select first and second clock signals between the N clock signals. Such that the phase shift delay between the two selected clock signals is representative of the non-integer value of K. The selected clock signals are combined to output a divided clock signal. The enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal.

A mixed rotative and weighted arbiter for arbitrating the priority of request signals R1-Rn supplied from a plurality of devices is disclosed. The arbiter is composed of a token circuit which delivers a token vector having one position set active. The token vector as well as the plurality of request signals are input to a rotative arbitration circuit. The rotative arbitration circuit processes a round robin algorithm to output a rotative request vector having input requests ordered from a higher to a lower priority configuration according to the active position of the token vector. The arbiter further comprises a weighted arbitration circuit connected to the output of the rotative arbitration circuit for generating a weighted request vector determining a linear priority configuration of the rotative request vector. A grant generation circuit is connected to the output of the weighted arbitration circuit and to the output of the token circuit to deliver a grant order to the device which may gain access to the bus and a plurality of no grant orders to the others devices.

Fair and high speed arbitration system based on rotative and weighted priority monitoring

A synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency is provided. The synchronization circuit is responsive to a control signal generated by memory status means coupled to a memory which temporarily stores data transmitted from the emitter bus to the receiver bus. The control signal representative of the status of the memory is reflecting asynchronous read and write operations within the memory. The resultant signal output from the synchronization circuit is a one clock synchronized signal such that rising and falling transitions are synchronized to the receiver bus clock frequency.

System and method for synchronizing data communication between asynchronous buses

An interrupt masker for use in an interrupt handler which receives interrupt request signals in the form of edge detection or level assertion is disclosed. The interrupt masker comprises interrupt detection means for detecting edge transitions of interrupt request signals. The interrupt masker also comprises a polarity detection means for detecting edge transitions of a polarity control signal which is inverted for each inversion polarity request. A filtering means which is coupled to the interrupt detection means and to the polarity detection means generates an interrupt request pulse according to the assertion of the polarity control signal. The interrupt request pulse is generated in response of either rising or falling edge transitions of the interrupt request signal.

Interrupt masker for an interrupt handler with double-edge interrupt request signals detection

Blocks of data are transferred in burst mode from a first device attached to a first bus, to a second device attached to a second bus having time multiplexed address/data lines. A bridge circuit includes an address register, which is coupled to the first bus, a circuit for incrementing the address register, and an output register coupled to the address/data lines of the second bus. In an aborted burst mode transfer of a block of data from one device to the other in which a 'last' data byte in the block was successfully transferred, but a 'next' byte of data was not successfully transferred, the system provides for an efficient retry of the transfer of the aborted data block. This efficient retry is accomplished in part by swapping the information in the address register of the bridge circuit with the information in its output register, such that the output register contains the address of the 'next' data byte. After the address of the 'next' data byte is placed on the second bus, a second swap occurs, such that the 'next' data byte itself is moved back into the output register.

Burst mode data transmission retry of previously aborted block transfer

A memory system with adaptable redundancy comprises address decoding means (200) for the selection of one of the rows R.sub.1 to R.sub.2 (n+1) in the memory array, according to the binary value of address A.sub.0, A.sub.1, . . . A.sub.nn incoming on bus 102. Block 200 comprises 2.sup.(n+1) blocks 201 being able to drive an activation signal on leads R.sub.1 to R.sub.2 (n+1), and having an output connected to a lead 206. Block 205 is able to drive an activation signal on lead RR according to signals present on leads 107 and 206, so as to select redundant row RR.sub.1 without the use of a redundant address decoder.

Memory system with adaptable redundancy

A combined sense amplifier and latching circuit receives an input signal (VIN) at an input terminal (22). A sense amplifier includes a gated-loop type master latch (ML) having two cascaded inverters (I12, I13) with a common node (I) coupled therebetween and a control device (TG4) in the master latch loop controlled by a gating signal (55A). A reference voltage generator generates a reference voltage (VREF). The two inverters are biased between a first supply voltage (Vdd) having a magnitude greater than the reference voltage and either a second supply voltage (GND) or the reference voltage depending on the value of the gating signal. The input terminal is connected to the input of one of the inverters. A gated-loop slave latch (SL) is connected in series with the sense amplifier and includes two cascaded inverters (I14, I15) with a common node (M) coupled therebetween and a control device (P15) in the slave latch loop controlled by the gating signal. The sense amplifier and the slave latch are isolated from each other by a control device (TG5) controlled by the gating signal.

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Maisons Alfort, France

Francis Bredin