International Business Machines Corporation

Francis A Kampf

Suzanne Granato

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Alan Frederic Benner

Douglas James Joseph

Jason Michael Norman

Christine M Desnoyers

Barbara L Powers

Douglas Thomas Massey

David Robert Stauffer

Jesse Ethan Craig

Peter Joel Jenkins

Jeanne Trinko-Mechler

Glen Alan Jaquette

Serafino Bueti

Oscar Conrad Strohacker

Adam J Courchesne

Rafael Blanco

Jonathan P Ebbers

Riyon W Harding

John Joseph Bergkvist, Jr

Gary R Doyle

Bruce J Ditmyer

Susan Farmer Bueti

Louis Stermole

An adaptive lossless data compression method for compression of color image data in a data processing system. The method includes comparing a plurality of components of a plurality of adjacent pixels in a digital image, calculating spatial differences between the plurality of adjacent pixels, encoding the spatial differences and recording the encoded spatial differences, formatting an image file representing the digital image into byte streams based on bit significance, and compressing, independently, the byte streams associated with each bit significance of the encoded spatial differences.

Adaptive lossless data compression method for compression of color image data

A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.

Simulation of digital circuits

Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Automated simulation testbench generation for serializer/deserializer datapath systems

The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.

Verifying non-deterministic behavior of a design under test

A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Generating test coverage bin based on simulation result

A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically coupling an output of the first source latch to a first input of the logic cone, and a WAGG circuit electrically coupling an output of the logic cone and an input of the first source latch. Then, a zero-delay simulation is performed in which if a first situation of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, the WAGG circuit generates a random value of 0 or 1 at the input of the destination latch.

Circuit design verification

A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is created for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.

Verification of the design of an integrated circuit background

Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

Fiber optic transmission lines on an SOC

A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.

Simulation testing of digital logic circuit designs

A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

Semiconductor device comprising a plurality of memory structures

A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

Reconfigurable circular bus

A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

System and method for correcting timing signals in integrated circuits

A method and system for increasing compression efficiency of a lossless data compression utility. The data compression utility compresses a segmented input data stream into independently decompressible data blocks, and includes a history buffer that maintains a history of matching character sequences. In accordance with the method of the present invention, a data segment is compressed utilizing a history buffer to identify repeated character sequences within the data segment. Upon receipt of a next data segment to be compressed, the history buffer is updated to include a pre-selected data set and reset data from the next data segment. As part of the compression an adaptable cache is searched for non-repeating bytes within a next data segment. Matching bytes are coded as cache references. Further efficiency is obtained by processing the next data segment as two-byte pairs.

Method and system for improving lossless compression efficiency

A program product for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages. The flow control technique disclosed herein is used, for example, in an environment where buffers are posted to accommodate messages at the destination node, and is particularly suited for conditions arising in multi-tasking systems where the destination node is generally assumed to be prepared to accommodate data, however, if not prepared, is likely not prepared for long periods of time.

Growing community of inventors

Jeffersonville, VT, United States of America

Francis A Kampf