Stmicroelectronics S.r.l.

Micron Technology Incorporated

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (rousset) Sas

Francesco Tomaiuolo

Salvatore Nicosia

Luca Giuseppe De Ambroggi

Antonino Mondello

Promod Kumar

Fabrizio Campanale

Carmelo Condemi

Marco Ruta

Antonino Conte

Tommaso Zerilli

Michelangelo Pisasale

Agatino Massimo Maccarrone

Luigi Pascucci

Salvatore Giove

Fabio Indelicato

Maria Luisa Gambina

Pierluca Guarino

Francesco La Rosa

Thomas Jouanneau

Giovanni Nunzio Maria Avenia

Carmela Maria Calafato

Alin Razafindraibe

Thibault Mortier

Antonio Conte

Diego De Costantini

Francesco Pipitone

Leonardo Valencia Rissetto

Pierpaolo Nicosia

Marion Helne Grimal

Vincenzo Russo

In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.

Non-volatile phase-change memory device including a distributed row decoder with n-channel MOSFET transistors and related row decoding method

A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.

Comparator systems and methods

A LDO regulator circuit comprises an input comparator and driver circuitry including transistors having a current flow path therethrough coupled to an output node of the regulator. First and second driver each comprises: driver transistors having the current flow paths therethrough coupled to the output node, capacitive boost circuitry that applies to the drive transistors a voltage-pumped replica of the comparison signal. Voltage refresh transistor circuitry coupled to the capacitive boost circuitry transfer thereon the voltage-pumped replica. The first and second drivers can be controllably switched between a first mode of operation, during which the current flow path through the driver transistors is conductive or non-conductive based on the voltage-pumped replica of the comparison signal, and a second mode, during which the voltage refresh transistor circuitry is activated to transfer the voltage-pumped replica of the comparison signal, and the current flow path through the driver transistors is non-conductive.

Low drop-out regulator circuit, corresponding device and method

In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current for the programming currents into the common control node.

Driver circuit for phase-change memory cells and method of driving phase-change memory cells

In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Digital-to-analog converter circuit

In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.

Method of data management for a bitwise programmable non-volatile memory, and corresponding device

In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.

An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.

Memory devices with cryptographic components

A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

Voltage regulator circuit and corresponding memory device

Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

Physical unclonable function with NAND memory array

An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

Monotonic counters in memories

Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Apparatuses and methods to perform continuous read operations

An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

Growing community of inventors

Monte Sant'Angelo, Italy

Francesco Tomaiuolo