Stmicroelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Stmicroelectronics N.v.

Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.r.l.

France Brevets

Francesco Pappalardo

Giuseppe Visalli

Giuseppe Notarangelo

Giuseppe Avellone

Agostino Galluzzo

Biagio Giacalone

Agatino Pennisi

Elio Guidetti

Davide Tesi

Elena Salurso

Francesco Rimi

Dario Di Bella

Vincenzo Matranga

Francesco Nino Mammoliti

Alessandro Capra

Francesco Bombaci

Luigi Mantellassi

Carmelo Marcello Palano

Massimo Mancuso

Giovanni Girlando

Giuseppe Spampinato

Liliana Arcidiacono

Daniele Lo Iacono

Francesca Grande

Michele Calabretta

Alberto Serratore

Claudio Luzzi

Edmondo Gangi

Paolo Antonino Foderá

Filippo Speziali

Francesco Maria Virlinzi

Vincenzo Catania

Enrico Pelos

Hervé Broquin

Angelo Doriani

Paolo Antonino Foderà

A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

System and method for clock resynchronization

A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.

Capacitive pressure sensor for monitoring construction structures, particularly made of concrete

A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

System related integrated circuit, apparatus and method

A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.

Receiver circuit, related integrated circuit and apparatus

A monitoring device is for a block of building material. The monitoring device may include an electric supply line configured to be buried in the block of building material and having a flexible main cable, and flexible jumper cables coupled to the flexible main cable and extending outwardly. The monitoring device may include sensor devices configured to be buried in the block of building material and coupled to respective ones of the flexible jumper cables. Each sensor device may include a primary inductor coupled to the electric supply line at a position based upon peaks of a stationary waveform when the electric supply line is alternating current (AC) powered, and a monitoring circuit. The monitoring circuit may include an integrated sensor, and a secondary inductor magnetically coupled to the primary inductor and configured to supply the integrated sensor, and communicate through the electric supply line.

Monitoring device with jumper cable coupling and related methods

Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

System for detecting operating errors in integrated circuits

Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: The processing step comprises the operations of:

Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method

A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.

Cache memory system and method with improved mapping flexibility

A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Method and arrangement for cache memory management, related processor architecture

A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.

Processor architecture with processing clusters providing vector and scalar data processing capability

Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Process and devices for transmitting digital signals over buses and computer program product therefore

A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Method and system for high-speed floating-point operations and related computer program product

A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

Multidimensional processor architecture

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Paterno, Italy

Francesco Pappalardo