International Business Machines Corporation

Francesco M Masci

Jack A Dorler

Dennis C Banker

Walter S Klara

This invention contemplates the provision of a noise immune integrated circuit receiver in which the voltage reference to one side of an emitter-coupled current switch moves in response to the input signal, in a direction opposite the input signal. This provides the gate with a threshold hysteresis, making it immune to noise without requiring a large swing in input signal.

High noise tolerance receiver

CMOSFETs control the power in a bipolar logic gate to regulate its operating speed and hence its delay. In a specific embodiment of the invention, an n-channel CMOSFET controls the constant current through an emitter-coupled current switch, comprised of a pair of bipolar integrated circuit transistors. A p-channel CMOSFET, in series with each collector of the switch pair, establishes the collector voltage so as to maintain constant the output swing of the gate as the power through the gate is varied in order to regulate the gate delay. An error signal, indicative of factors that can cause variations in gate delay and the inverse of the error signal are generated by an on-chip circuit. The error signal is coupled to the n-channel CMOSFET and the inverse of the error signal is coupled to the p-channel CMOSFET. Thus, as the switch current is decreased in order to increase the gate delay, the collector impedance is simultaneously increased so the collector voltage, and hence the gate swing, remains constant. Similarly, when the switch current is increased, the collector impedance is decreased.

BICMOS ECL circuit suitable for delay regulation

A high performance bipolar, field effect transistor (BiFET) logic circuit has minimal power supply requirements, allowing the circuit to be manufactured in higher density devices than current switched emitter follower (CSEF). BiFET logic circuit has a plurality of input lines and first and second output lines. A plurality of FET devices are connected in parallel each having a gate connected to a corresponding one of the input lines. Two bipolar transistors are connected as a differential pair, the parallel connection of said FET devices providing an input to the base of the first bipolar transistor while the base of the second bipolar transistor is supplied with a reference voltage. Output bipolar transistors connected as emitter followers drive the first and second output lines respectively. One of these output bipolar transistors is driven by the first bipolar transistor of the differential pair, while the other of the output bipolar transistors is driven by the second bipolar transistor of the differential pair. By dotting the collectors of the differential pair, as is commonly done in CSEF circuits, additional logic functions are obtained; however, the number of additional logic functions obtained is greater than that obtainable in CSEF circuits. Thus, the BiFET has the additional advantage of providing additional logic function and flexibility as compared with CSEF circuits.

Growing community of inventors

Wappingers Falls, NY, United States of America

Francesco M Masci