Xerox Corporation

Nanosys, Inc.

Innovalight, Inc.

Oned Material, Inc.

Francesco Lemmi

Jeng Ping Lu

Christopher L Chua

Eric Peeters

Decai Sun

David Kirtland Fork

Linda T Romano

Ping Mei

David P Stumbo

Robert Anthony Street

Donald Leonard Smith

James B Boyce

Koenraad F Van Schuylenbergh

Patrick Yasuo Maeda

Xiangfeng Duan

Elena Rogojina

Homer Antoniadis

Maxim Kelman

David Carl Jurbergs

Yaoling Pan

James M Hamilton

Pingrong Yu

Cheri X Y Pereira

J Wallace Parce

Robert S Dubrow

Erik C Scher

Chunming Niu

Jian Chen

Stephen A Empedocles

Jeffery A Whiteford

Karel Vanheusden

Francisco A Leon

Scott Eugene Solberg

Michel A Rosa

Jay L Goldman

Vijendra Sahi

Dmitry Poplavskyy

David Leslie Heald

Andreas Meisel

Jeffrey L Miller

Harry Jonathan McIntyre

George Pontis

JengPing Lu

David Dutton

Malcolm Abbott

Mason Terry

Paul Bernatis

Alice Fischer-Colbrie

Cheri XY Pereira

Harry J Mcintyre

The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Methods for formation of substrate elements

A method of forming a densified nanoparticle thin film is disclosed. The method includes positioning a substrate in a first chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30&#xb0; C. and about 300&#xb0; C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed; and positioning the substrate in a second chamber, the second chamber having a pressure of between about 1&#xd7;10Torr and about 1&#xd7;10Torr. The method further includes depositing on the porous compact a dielectric material; wherein the densified nanoparticle thin film is formed.

Methods of filling a set of interstitial spaces of a nanoparticle thin film with a dielectric material

The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.

Systems and methods for harvesting and integrating nanowires

Nanowire dispersion compositions (and uses thereof) are disclosed comprising a plurality of inorganic nanowires suspended in an aqueous or non-aqueous solution comprising at least one low molecular weight and/or low HLB (Hydrophile-Lipophile Balance) value dispersant. Methods of further improving the dispersability of a plurality of inorganic nanowires in an aqueous or non-aqueous solution comprise, for example, oxidizing the surface of the nanowires prior to dispersing the nanowires in the aqueous or non-aqueous solution.

Nanowire dispersion compositions and uses thereof

Systems and methods for harvesting and reducing contamination in nanowires

A method for forming a contact to a substrate is disclosed. The method includes providing a substrate, the substrate being doped with a first dopant; and diffusing a second dopant into at least a first side of the substrate to form a second dopant region, the first side further including a first side surface area. The method also includes forming a dielectric layer on the first side of the substrate. The method further includes forming a set of composite layer regions on the dielectric layer, wherein each composite layer region of the set of composite layer regions further includes a set of Group IV semiconductor nanoparticles and a set of metal particles. The method also includes heating the set of composite layer regions to a first temperature, wherein at least some composite layer regions of the set of composite layer regions etch through the dielectric layer and form a set of contacts with the second dopant region.

Methods for forming composite nanoparticle-metal metallization contacts on a substrate

A method of forming a densified nanoparticle thin film in a chamber is disclosed. The method includes positioning a substrate in the chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30&#xb0; C. and about 300&#xb0; C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes exposing the porous compact to an HF vapor for a second time period of between about 2 minutes and about 20 minutes, and heating the porous compact for a second temperature of between about 25&#xb0; C. and about 60&#xb0; C.; and heating the porous compact to a third temperature between about 100&#xb0; C. and about 1000&#xb0; C., and for a third time period of between about 5 minutes and about 10 hours; wherein the densified nanoparticle thin film is formed.

Methods for creating a densified group IV semiconductor nanoparticle thin film

A structure and method for suppressing lateral leakage current in full fill factor image arrays includes dual dielectric passivation layer. A first passivation layer includes a material that is an insulator, has a low dielectric constant to minimize capacitive coupling between the contacts, and is low stress to prevent cracking. A second passivation layer includes a thin oxide or nitride layer over the first passivation layer.

Dual dielectric structure for suppressing lateral leakage current in high fill factor arrays

An out-of-plane micro-structure which can be used for on-chip integration of high-Q inductors and transformers places the magnetic field direction parallel to the substrate plane without requiring high aspect ratio processing. The photolithographically patterned coil structure includes an elastic member having an intrinsic stress profile. The intrinsic stress profile biases a free portion away from the substrate forming a loop winding. An anchor portion remains fixed to the substrate. The free portion end becomes a second anchor portion which may be connected to the substrate via soldering or plating. A series of individual coil structures can be joined via their anchor portions to form inductors and transformers.

Method of making photolithographically-patterned out-of-plane coil structures

A light-producing device integrated with a power monitoring system include a light-producing device from which light is emitted in wavelengths that can range from approximately 700 nm to approximately 3 microns. A semi-transparent sensor is located such that at least a portion of the light emitted passes through the semi-transparent sensor and at least a portion of light is absorbed by the semi-transparent sensor. The semi-transparent sensor is configured to be semi-transparent at wavelengths that can range from 700 nm to 3 microns. The semi-transparent sensor may also be used with an external light source, for example with fiber-optic cables.

Semi-transparent power monitor integrated with a light producing module

Photolithographically-patterned out-of-plane coil structures and method of making

A hybrid structure or device is provided wherein carried on a single substrate is at least one micro-spring interconnect having an elastic material that is initially fixed to a surface of the substrate, an anchor portion which is fixed to the substrate surface and a free portion. The spring contact is self-assembling in that as the free portion is released it moves out of the plane of the substrate. Also integrated on the substrate is a sensor having an active layer and contacts. The substrate and sensor may be formed of materials which are somewhat partially transparent to light at certain infrared wavelengths. The integrated sensor/spring contact configuration may be used in an imaging system to sense output from a light source which is used for image formation. The light source may be a laser array, LED array or other appropriate light source. The sensor is appropriately sized to sense all or some part of light from the light source. The sensor may also be sufficiently transparent so that light is not blocked from its emission path, with a contrast ratio such that it only absorbs a small fraction of light passing therethrough. An additional characteristic is that the manufacturing process is compatible with the manufacturing process for the micro-spring interconnects. Data from the sensor is used as light source correction information. This information is provided to a calibration configuration which allows for calibration of high-speed systems.

Amorphous silicon sensor with micro-spring interconnects for achieving high uniformity in integrated light-emitting sources

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Sunnyvale, CA, United States of America

Francesco Lemmi