Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics International N.v.

Francesco La Rosa

Stephan Niel

Arnaud Regnier

Antonino Conte

Julien Delalleau

Marc Mantelli

Gineuve Alieri

Enrico Castaldo

Thierry Giovinazzi

Pascal Fornara

Philippe Boivin

Raul Andres Bianchi

Francesca Grande

Marco Bildgen

Jimmy Fort

Jean-Michel Mirabel

Nicolas Borrel

Alfredo Signorello

Yoann Goasduff

Santi Nunzio Antonino Pagano

Filipe Ganivet

François Tailliet

Mathieu Pierre Lisart

Alexandre Sarafianos

Francesco Tomaiuolo

Paola Cavaleri

Gianbattista Lo Giudice

Giovanni Matranga

Maria Giaquinta

Laurent Lopez

Giuseppe Nastasi

Olivier Pizzuto

Francois Maugain

Franco Italiano

Hélène Dalle-Houilliez

Thierry Soudé

In an embodiment a method for convolutional computation (CNVL) of input values with weight factors includes converting the input values to voltage signals and successively applying the voltage signals on selected bit lines in an array of non-volatile memory points over respective time slots, each memory point comprising a phase-change resistive memory cell coupled to a bit line and having a resistive state corresponding to a weight factor, and a bipolar selection transistor coupled in series with the phase-change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signals bias the respective phase-change memory cells, integrating over the successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines and converting the integrated read currents to output values.

Method for in-memory convolutional computation and corresponding integrated circuit

In an embodiment a device includes a supply node configured to receive a supply voltage, an output node configured to provide an output voltage, a plurality of switching stages coupled to the supply node and to the output node, a sensing circuit coupled to the supply node and configured to provide at least one sensing signal based on the supply voltage and a driver circuit coupled to the sensing circuit and to the plurality of switching stages, wherein the driver circuit is configured to provide the drive signal based on at least one sensing signal exceeding or failing to exceed at least one reference voltage level and to selectively bypass a selected number of the plurality of switching stages based on the drive signal thereby varying an output voltage level at the output node.

Voltage regulator device, corresponding method and data storage system

The present description concerns an electronic device including: a first input configured to receive a clock signal, coupled by a first input buffer to a first circuit; and at least an output coupled by an output buffer to the first circuit, the output buffer being synchronized on first edges of the clock signal, wherein the first input buffer includes a data input coupled to the first input and is configured to maintain the value on its output constant whatever the value on its data input during a duration following each first edge of the clock signal.

Device with synchronous output

An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

Protection of an integrated circuit

Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.

Integrated circuit including a physically unclonable function device and corresponding method for implementing a physically unclonable function

In an embodiment a method programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors, performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage, performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive and outputting output values resulting from the convolutional computation.

Method and apparatus for convolutional computation based on floating gate NVM array

In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

Physically unclonable function device

In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

Non-volatile memory device readable only a predetermined number of times

In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.

Non-volatile memory device with improved cell cycling and corresponding method for operating the non-volatile memory device

An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.

Physical unclonable function device and method

A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

Method for writing in a non-volatile memory according to the ageing of the memory cells and corresponding integrated circuit

In accordance with an embodiment, a physically unclonable function device includes a set of floating gate transistor pairs, floating gate transistors of the set of floating gate transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of floating gate transistor pairs of the set of floating gate transistor pairs, and to identify a floating gate transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable floating gate transistor pair; and a write circuit configured to shift the effective threshold voltage of a floating gate transistor of the unreliable floating gate transistor pair to be inside the common random distribution.

Device of physically unclonable function with floating gate transistors, and manufacturing method

In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.

Device of physically unclonable function with transistors, and manufacturing method

An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

Power-on-reset circuit and corresponding electronic device

A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.

Growing community of inventors

Rousset, France

Francesco La Rosa