Stmicroelectronics S.r.l.

Stmicroelectronics (grenoble 2) Sas

Francesco Giotta

Salvatore Pisasale

Giuseppe Guarnaccia

Riccardo Locatelli

Michael Soulie

Giuseppe Falconeri

Raffaele Guarrasi

Marco Castano

Carmine Ciofi

A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

Method and apparatus for supporting reprogramming or reconfiguring

An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data.

Interfacing device and method, for example for systems-on-chip

A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies. The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, a maximum rate of the data transfer, with the rate being a function of all the possible input and output delays supported by the SoC. This is dependent on the parameters of the SoC. There is also a phase for programming a generic frequency converter between the first and second integrated processors for the data transfer, and a phase for scheduling the data transfer between the semi-synchronous clock domains.

Method for improving the data transfer in semi synchronous clock domains integrated circuits at any possible m/n clock ratio

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Catania, Italy

Francesco Giotta