Micron Technology Incorporated

Lodestar Licensing Group LLC

Francesco Falanga

Massimo Iaculo

Danilo Caraccio

Francesco Basso

Pasquale Cimmino

Victor Y Tsai

Eric Kwok Fung Yuen

Angelo Della Monica

Antonino Pollio

Emanuele Confalonieri

Luca Porzio

Nadav Grosz

Giuseppe D'Eliseo

Roberto Izzi

Giuseppe Ferrari

Alberto Sassara

Ornella Vitale

Crescenzo Attanasio

Nicola Cavaliere

Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

Idle mode temperature control for memory systems

Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.

Read disturb management for memory

Memory devices might include an array of memory cells, a register, and a controller for access of the array of memory cells. The controller might be configured to autonomously perform background operations on the array of memory cells in response to the register storing a first value, and prohibit autonomous performance of the background operations on the array of memory cells in response to the register storing a second value different than the first value. The memory devices might be in communication with a host.

Memory devices and systems for host controlled enablement of automatic background operations in a memory device

Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.

Data caching for fast system boot-up

Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses

A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Virtual partition management

Methods, systems, and devices for an enhanced instruction caching scheme are described. A memory controller may include a first closely-coupled memory component that is associated with storing data and control information and a second closely-coupled memory component that is associated with storing control information. The memory controller may be configured to retrieve data from the first memory closely-coupled component and control information from a second closely-coupled memory component. Control information may be stored in the first closely-coupled memory component, and a memory controller may access the control information stored in the first closely-coupled memory component by transferring, from the first closely-coupled memory component, the control information into the second closely-coupled memory component. After transferring the control information into the second closely-coupled memory component, the memory controller may access the control information from the second closely-coupled memory component.

Instruction caching scheme for memory devices

Virtual partition management in a memory device

Methods for automatically performing a background operation in a memory device might include automatically performing the background operation responsive to automatic performance of the background operation being enabled and receiving a start command.

Host controlled enablement of automatic background operations in a memory device

A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

Autorecovery after manufacturing/system integration

Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells. The control circuitry is further configured to perform a test of the particular data in response to a command received from an external device and perform a repair of the particular data when results of the test indicate that repair of the particular data is needed

Growing community of inventors

Pozzuoli, Italy

Francesco Falanga