Texas Instruments Corporation

Francesco Dantoni

Samuel D Pritchett

Jeffrey A Schlang

Robert Clair Keller

Jaiganesh Balakrishnan

Visvesvaraya Appala Pentakota

Jawaharlal Tangudu

Anil K V Kumar

Sandeep Kesrimal Oswal

Jagannathan Venkataraman

Sarma Sundareswara Gunturi

Naveen Krishna Yanduru

Ranjit Gharpurey

Nagarajan Viswanathan

Petteri Matti Litmanen

Yeswanth Guntupalli

Salvatore Luciano Finocchiaro

Shrinivasan Jaganathan

Alan R Holden

Sherif Embabi

Raju Kharataram Chaudhari

Wenjing Lu

Kalyan Gudipati

Thomas R Neu

Harsh Garg

Bragadeesh S

Michael James Arnold

An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.

Dual-band AGC for RF sampling receivers

A system includes: a host processor; a transceiver coupled to the host processor; and a power amplifier coupled to an output of the transceiver. The transceiver includes a transmit chain with digital pre-distortion (DPD) logic configured to: perform DPD correction operations on transmit data received by the transmit chain; and output corrected transmit data based on the performed DPD correction operations, wherein the output corrected transmit data is provided to the power amplifier.

Transceiver circuit with digital pre-distortion (DPD) options

A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

RF transmitter and auxiliary receiver to capture transmit signal data to compensate for transmit signal impairments

Apparatus and methods disclosed herein implement an RF receive-band filter at a receive chain input of a wireless base station with a co-located transmitter and receiver. The RF receive-band filter includes an adaptive filter component to perform filtering operations on samples of a digital baseband or intermediate frequency signal x(n) from a transmit chain associated with the wireless base station. An adaptive filter transfer function is determined in real time such that samples of the baseband transmit signal x(n) are transformed into a cancellation baseband signal z(n). The digital cancelation baseband signal z(n) is then digital-to-analog converted and the resulting analog baseband signal z(t) is up-converted to obtain a subtractive RF cancelation signal c(t). C(t) is summed with a desirable received signal RF component r(t) and an undesirable transmitter leakage RF signal component l(t) appearing at the input to the base station receiver. C(t) cancels l(t), leaving r(t) to be processed by the receiver section of the base station.

Transmit signal cancelation apparatus and methods

Baseband processor and communication overloading can be relieved in a portable wireless communication terminal by decentralizing power control () and frequency shift control () functions that are conventionally concentrated in the baseband processor. A timing sequencer () for power control can be integrated into a transceiver of the portable wireless communications terminal, thereby advantageously permitting power control signals to be generated on the transceiver side () rather than the baseband processor side. Shadow registers () containing information indicative of commonly used or repeated frequencies can be integrated into the transceiver side, thereby advantageously relieving the baseband processor of corresponding frequency shift control responsibilities. These responsibilities can be further relieved by integrating into the transceiver side a sequencer () cooperable with the shadow registers for controlling frequency shifting of a frequency generator on the transceiver side, and by integrating into the transceiver side further shadow registers () for programming the sequencer with desired frequency shift sequences.

Wireless communications with transceiver-integrated frequency shift control and power control

In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Open loop coarse tuning for a PLL

A system for controlling carrier leakage in a communications device includes a first mixer unit operable to receive and convert a first signal into a second signal having a higher frequency than the first signal, and to transmit the second signal, a second mixer unit operable to receive, convert the second signal into an in-phase signal and a quadrature signal each having lower frequency than the second signal, and transmit them, a processor coupled to the first mixer and the second mixer to perform a leakage reduction procedure by receiving and sampling the in-phase signal and the quadrature signal, determining that a result from the sampling is not equal to a predetermined value, initiating a transmission of a direct current offset signal to the first mixer unit, and adjusting a voltage of the direct current offset signal until a next result of the sampling approximately equals the predetermined value.

Method and system for controlling carrier leakage in a direct conversion wireless device

Methods and apparatus to pre-compensate for in-phase/quadrature (I/Q) distortion in quadrature transmitters are disclosed. A disclosed example method comprises coupling a portion of an analog baseband in-phase signal to an analog baseband quadrature signal through an impedance, and selecting a resistance value for the impedance to pre-distort the analog baseband quadrature signal to compensate for an error introduced by modulation of the analog baseband in-phase signal and the analog baseband quadrature signal.

Methods and apparatus to pre-compensate for I/Q distortion in quadrature transmitters

An RF receiver apparatus () is provided physically separately from a cooperating baseband processor apparatus (). The RF receiver includes a mixer circuit () and an analog IF-to-digital baseband converter () formed on an integrated circuit. Sampling frequencies of the analog IF-to-digital baseband converter are controlled by the RF receiver apparatus.

If-to-baseband conversion for flexible frequency planning capability

According to one embodiment of the invention, a system for controlling carrier leakage in a communications device is provided. The system includes a first mixer unit operable to receive a first signal, to convert the first signal into a second signal having a higher frequency than the first signal, and to transmit the second signal. The system also includes a second mixer unit. The second mixer unit is operable to receive the second signal, to convert the second signal into an in-phase signal and a quadrature signal each having lower frequency than the second signal, and to transmit the in-phase signal and the quadrature signal. The system also includes a processor coupled to the first mixer and the second mixer. The processor is operable to perform a leakage reduction procedure by receiving the in-phase signal and the quadrature signal from the second mixer, sampling the in-phase signal and the quadrature signal, determining that a result from the sampling is not equal to a predetermined value, initiating a transmission of a direct current offset signal to the first mixer unit, and adjusting a voltage of the direct current offset signal until a next result of the sampling approximately equals the predetermined value.

A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up mode signal controls electronics associated with one or more amplifiers to facilitate settling time of an output signal of the amplifier(s) that occurs when the gain of the amplifier changes. The gain control signal also can be delayed to provide a delayed version of the gain control signal for controlling gain of the amplifier(s).

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Rome, Italy

Francesco Dantoni