Stmicroelectronics S.r.l.

Stmicroelectronics (rousset) Sas

Francesco Bombaci

Francesco Pappalardo

Santi Carlo Adamo

Davide Tesi

Francesco Nino Mammoliti

Vincent Onde

Alessandro Inglese

Rosalino Critelli

Ugo Mari

Pietro Cusmano

Orazio Musumeci

Sonia Sfasciotti

Gianluca Vincenzo Aureliano

Andrea Tosoni

A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.

System-on-chip comprising a non-volatile memory

A communication system for an HDMI communication interface CEC channel includes a communication module for receiving messages via the CEC channel, a processing unit for processing the received messages and an oscillator for driving the communication module. When the interface is in an active mode, the system is operative to activate the timer upon detection of the start of transmission of a first message, detect the initial bit of the first message, reconstruct and process the first message, and switch the interface from the active mode to standby by deactivating the oscillator. When the interface is in standby, the system is operative to switch the interface to the active condition by activating the oscillator and the timer when the start of a transmission of a second message is detected, detect the initial bit of a transmission of the second message, and reconstruct and process the second message.

Communication system for a control channel, and corresponding method and computer program product

An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.

Analog-digital converter and corresponding system and method

A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.

Method and system for configuring registers in microcontrollers, and corresponding computer-program product

A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references is provided. The digital interface includes a first input terminal for receiving a PWM input signal, a first counter stage connected to the first input terminal, and a second counter stage connected to an output of the first counter stage. A toggle stage is connected to the first input terminal and to an output of the second counter stage. A first output terminal is connected to an output of the toggle stage, and is to be connected to a control terminal of the first power element. A second output terminal is connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and is to be connected to a control terminal of the second power element. The toggle stage generates a second PWM output signal for the first output terminal. The second PWM output signal is kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.

Digital interface for driving at least a couple of power elements, in particular in PWM applications

A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Direct control of operation blocks using operand signal of control instruction as extension to instruction set in a hardwired control processor

A processor is provided with a set of instructions formed in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Growing community of inventors

Messina, Italy

Francesco Bombaci