International Business Machines Corporation

Francesco A Campisano

David Allen Hrusecky

Dennis P Cheney

Michael Stephen Floyd

Alan J Drake

Xiaobin Yuan

Chuck Hong Ngai

David T Hui

Pawel Owczarczyk

Marshall Dale Tiner

Ronald S Svec

Bryan J Lloyd

Phillip John Restle

Gregory Scott Still

Brian Thomas Vanderpool

Eric Jason Fluhr

Richard L Willaman

Rahul Batra

Isidore G Bendrihem

Ian Krispin Carmichael

Eric Marz

Michael N Goulet

Rory Tatum

Providing deterministic frequency and voltage enhancements for a processor is disclosed. In an embodiment, a microcontroller on a processor identifies a plurality of parameters related to a processor, the plurality of parameters including at least a current supplied to the processor; determines, in dependence upon the plurality of parameters, one or more frequency scaling indexes including determining an effective switching capacitance ratio; identifies, in dependence upon the one or more frequency scaling indexes, a predetermined frequency parameter for the processor; and transitions, based on the frequency parameter, the processor to a target clock frequency. In another embodiment, a microcontroller on a processor decreases, incrementally, a power supply voltage for a processor; determines that a voltage droop parameter exceeds a voltage droop parameter threshold; and increases, incrementally, the power supply voltage in response to determining that the voltage droop parameter exceeds a voltage droop parameter threshold.

Providing deterministic frequency and voltage enhancements for a processor

An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Multi-core dynamic frequency control system

Trick mode playback is implemented by disengaging a frame synchronization signal, and then decoding 'I' and 'P' frames to two (or more) buffers. Specifically, each buffer has a pointer that is associated with a memory/origin address. The pointers are locked in place by disengaging the frame synchronization signal. Once the pointers are locked in place, the &#x201c;I&#x201d; frames and &#x201c;P&#x201d; frames are decoded to the two buffers in an alternating fashion based on a continuous swapping of the memory addresses associated with the two pointers. Because both &#x201c;I&#x201d; and &#x201c;P&#x201d; frames (as opposed to only &#x201c;I&#x201d; frames) are decoded and displayed, the trick mode playback appears smoother. In addition, because the frame synchronization signal was disengaged, the frames can be decoded at a rate faster than a single frame time. That is, one frame need not be completely decoded and read out before the next frame is decoded.

MPEG-2 decoder, method and buffer scheme for providing enhanced trick mode playback of a video stream

Loss of decoding time prior to the vertical synchronization signal when motion video is arbitrarily scaled and positioned by placing the frame switch point at the completion of frame decoding and synchronizing the bottom border of the scaled image therewith while maintaining low latency of decoded data. High latency operation is provided only when necessitated by minimal spill buffer capacity and in combination with fractional image size reduction in the decoding path in order to maintain image resolution without requiring additional memory.

Low latency video decoder with high-quality, variable scaling and minimal frame buffer memory

A digital video stream is digitally scaled to properly display on a device having a horizontal to vertical aspect ratio different than the source aspect ratio leaving a blank area on the device. Graphic data is digitally scaled separately to extend partially or completely into and therefore use the blank area. A compositing blender digitally combines the two prior to a display encoder which produces analog signals for driving the display device.

Digital video data scaler and method

A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames. The full size I and P frames are used to support future decode operations, while the scaled I, P & B frames are retrieved for display.

MPEG video decoder with integrated scaling and display functions

Growing community of inventors

Austin, TX, United States of America

Francesco A Campisano