Stmicroelectronics S.r.l.

Francesca Milanesi

Paolo Colpani

Samuele Sciarrillo

Ivan Venegoni

Francesco Maria Pipia

Annamaria Votta

Vincenzo Palumbo

Paolo Iuliano

Sonia Pirotta

Lucrezia Guarino

Claudio Zafferoni

A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.

Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation

An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

Semiconductor device and a corresponding method of manufacturing semiconductor devices

A semiconductor device including: a semiconductor body having a first side and a second side opposite to one another; a first barrier element, which extends over the first side of the semiconductor body and is made of a first material configured to act as barrier against metal ions, for example chosen from among titanium, tantalum, titanium alloys or compounds, tantalum alloy; a magnetic element, which extends over the first barrier layer and is made of a second material having magnetic properties, for example a ferromagnetic material; a second barrier element, which extends over the magnetic layer and is made of a third material configured to act as barrier against metal ions, for example chosen from among titanium, tantalum, titanium alloys or compounds, tantalum alloys or compounds. The first and second barrier elements form a top encapsulating structure and a bottom encapsulating structure for the magnetic element.

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Milan, Italy

Francesca Milanesi