Imec

Globalfoundries Inc.

Dow Corning Corporation

Katholieke Universiteit Leuven

Interuniversitair Microelektronica Centrum (imec)

Francesca Iacopi

Philippe Vereecken

Anne S Verhulst

Arturo Sibaja-Hernandez

Johan Adriaan Martens

Karen Irma Maex

Mikhail Rodionovich Baklanov

Serge Vanhaelemeersch

William Kenneth Weidner

Mikhaïl Baklanov

Frank Holsteyns

Salvador Eslava Fernandez

Christine Kirschhock

Stephane Malhouitre

Herman Meynen

A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 10atoms/cmto be obtained.

Doping of nanostructures

A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value Tand setting the pressure of the environment to a value P, contacting the surface with a fluid having a solidifying temperature at the pressure value Pabove the value Tand having a vaporizing temperature at the pressure value Pbelow 80&#xb0; C., thereby solidifying the fluid in pores of the material, thereby sealing the pores, treating the surface, wherein the treatment is preferably an etching or a modification of the surface, and setting the temperature of the surface to a value Tand setting the pressure of the environment to a value Pin such a way as to vaporize the fluid.

Protective treatment for porous materials

A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Control of tunneling junction in a hetero tunnel field effect transistor

Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Method of making a hetero tunnel field effect transistor

The present invention provides a method for forming a layer () of polycrystalline semiconductor material on a substrate (). The method comprises providing at least one catalyst particle () on a substrate (), the at least one catalyst particle () comprising at least a catalyst material, the catalyst material having a melt temperature of between room temperature and 500&#xb0; C., or being able to form a catalyst material/semiconductor material alloy with a eutectic temperature of between room temperature and 500&#xb0; C., and forming a layer () of polycrystalline semiconductor material on the substrate () at temperatures lower than 500&#xb0; C. by using plasma enhancement of a precursor gas, thereby using the at least one catalyst particle () as an initiator. The present invention furthermore provides a layer () of polycrystalline semiconductor material obtained by the method according to embodiments of the present invention.

Low-temperature formation of layers of polycrystalline semiconductor material

A method is provided for making pure-silica-zeolite films useful as low-k material, specifically, more hydrophobic, homogeneous and with absence of cracks. The method utilizes a UV cure; preferably the UV cure is performed at temperatures at higher than the deposition temperature. The UV-assisted cure removes the organic template promoting organic functionalization and silanol condensation, making the silica-zeolite films more hydrophobic. Moreover, the zeolite material is also mechanically stronger and crack-free. The method can be used to prepare pure-silica-zeolite films more suitable as low-k materials in semiconductor processing.

UV light exposure for functionalization and hydrophobization of pure-silica zeolites

A method for determining the presence of defects in a covering layer overlying an underlying layer in accordance with an embodiment of the invention comprises providing a substrate comprising the covering layer, where the covering layer is at least partially exposed. The covering layer is subjected to a first substance, such as a solvent, and then subjected to a light beam. An optical property of the covering layer is determined and compared with a threshold value. The presence of defects in the covering layer is determined by the difference of the optical property from the threshold value, where the optical property indicates a level of penetration of the first substance through the covering layer.

Method and apparatus for defect detection

A sealing dielectric layer is applied between a porous dielectric layer and a metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and sidewalls of the porous dielectric layer. This invention allows the use of a thin metal diffusion barrier layer without creating pinholes in the metal diffusion barrier layer. The sealing dielectric layer is a CVD deposited film having the composition Si C :H .

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Leuven, Belgium

Francesca Iacopi