Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

St-ericsson Sa

Francesca Girardi

Marco Zamprogno

Pierangelo Confalonieri

Germano Nicollini

Giuseppe Desoli

Thomas Boesch

Alberto Minuti

Angelo Nagari

Ruggero Susella

Paolo Sergio Zambotti

An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons.

Method for digital error correction for binary successive approximation analog-to-digital converter (ADC)

An electronic analog-to-digital conversion device includes an analog-to-digital conversion block having a first input for receiving a voltage signal to be converted based on a reference voltage signal provided to a second input, and an input block connected to the first input of the analog-to-digital conversion block. The input block receives an input signal at a first resistive network connected to a second resistive network, which is then connected to a reference potential. The input block also includes an active network connected between an output of the first resistive network and the first input of the analog-to-digital conversion block. The active network has a first input terminal directly connected to the second input of the analog-to-digital conversion block for receiving the same reference voltage signal so that the input voltage signal received at a second input of the active network is processed based on the reference voltage signal.

Analog-to-digital conversion device

According to a method of Successive Approximation Register (SAR) analog to digital conversion, N+1 SAR cycles are performed to obtain an output digital code having N bits. An analog signal is sampled and obtained. After execution of the first N&#x2212;1 SAR cycles, the NSAR cycle is performed by setting a Ntentative analog signal corresponding to a provisional digital code and comparing the Ntentative analog signal with the sampled analog signal to obtain a Ncomparison result. The (N+1)SAR cycle is performed by setting a (N+1)tentative analog signal based on the Ncomparison result, comparing the (N+1)tentative analog signal with the sampled analog signal to obtain a second comparison result, and correcting the provisional digital code based on the (N+1)comparison result to obtain the output digital code. The Nand (N+1)SAR cycles each comprise a plurality sub-comparisons and yield a set of sub-results.

Method of successive approximation A/D conversion

An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.

Analog digital converter

A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.

Circuit for selectively analog signals into digital codes

The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.

Analog-digital converter

The described converter comprises switched-capacitor quantization means for receiving an analog quantity to be converted, a register for a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means capable of responding to a conversion request signal by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register the digital quantity to be furnished as output. With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals emitted by the logic means. Also described is a method of using the converter that comprises the following phases: loading of the analog quantity in the quantization means, memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means.

Low consumption and low noise analog-digital converter of the SAR type and method of employing it

A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.

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Milan, Italy

Francesca Girardi