Stmicroelectronics S.r.l.

Francesca Giacoma Mignemi

Ranieri Guerra

Osvaldo Enrico Zambetti

Marco Leo

Nunzio Greco

Leandro Grasso

Enea Dimroci

Roberta Priolo

Francesco Battini

Serena Angela Versace

In accordance with an embodiment, a method of operating a buck-boost power supply includes operating the buck-boost power supply in a buck mode by providing a PWM signal to a first half-bridge circuit, and turning on a charge transfer switch coupled between a first boosted supply node of a second driver circuit coupled to the first half-bridge circuit and a second boosted supply node of a second driver circuit coupled to a second half-bridge circuit when a voltage between the second boosted supply node and an output of the second half-bridge circuit is below a first threshold; and operating the buck-boost power supply in a boost mode by providing a PWM signal to the second half-bridge circuit, and turning on the charge transfer switch when the voltage between the first boosted supply node and an output of the first half-bridge circuit is below a second threshold.

Buck-boost boot refresher circuit

A buck-boost converter circuit includes a mode selection circuit that asserts a buck enable signal if an input voltage is higher than a lower threshold, and asserts a boost enable signal if the input voltage is lower than an upper threshold. A control circuit asserts a buck PWM signal upon a pulse in a buck clock and de-asserts the buck PWM signal if a buck ramp is higher than a buck control signal, and it keeps the buck PWM signal asserted if the buck enable signal is de-asserted. The control circuit asserts a boost PWM signal upon a pulse in a boost clock and de-asserts the boost PWM signal if a boost ramp is higher than a boost control signal, and it keeps the boost PWM signal de-asserted if the boost enable signal is de-asserted.

Buck-boost DC-DC converter circuit and corresponding method of operation

A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

Systems and methods to test an asynchronous finite machine

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S. Giovanni La Punta, Italy

Francesca Giacoma Mignemi