Intel Corporation

Other

Imtel Corporation

Francesc Guim Bernat

Kshitij Arun Doshi

Karthik Kumar

Ned M Smith

Thomas Willhalm

Suraj Prabhakaran

Mark A Schmisseur

Timothy Verrall

Susanne M Balle

Daniel Rivas Barragan

Alexander Bachmutsky

Evan Custodio

Slawomir Putyrski

Raj K Ramanujan

Kapil Sood

Rajesh Poornachandran

Sujoy Sen

Marcos Emanuel Carranza

Andrew J Herdrich

Rahul Khanna

Raghu R Kondapalli

Brinda Ganesh

S M Iftekharul Alam

Tarun Viswanathan

Satish Chandra Jha

Henry M Mitchel

Christian Maciocco

John Joseph Browne

Vesh Raj Sharma Banjade

Dario Sabella

Narayan Ranganathan

Patrick G Kutch

Paul H Dormitzer

Vincent J Zimmer

Nageen Himayat

Robert G Blankenship

Murugasamy K Nachimuthu

Srikathyayani Srikanteswara

Edwin Verplanke

Miltiadis Filippou

Mohan J Kumar

Mats Gustav Agerstam

Lidia Warnes

Yi Zhang

Durgesh Srivastava

Ramanathan Sethuraman

Thijs Metsch

Rita H Wouhaybi

Liuyang L Yang

Katalin Klara Bartfai-Walcott

Sanjay Bakshi

Vadim Sukhomlinov

Mona Vij

Kuilin Clark Chen

Dimitrios Ziakas

Nilesh K Jain

Ravishankar Iyer

Hassnaa Moustafa

Mark D Yarvis

Eve M Schooler

Vinodh Gopal

Ravi L Sahita

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Ren Wang

Patrick L Connor

Arvind Srinivasan

Vincent R Scarlata

Alex Nayshtut

Yang-Seok Choi

Ignacio Javier Alvarez

Farid Adrangi

Pete D Vogt

David Israel Gonzalez Aguirre

David A Koufaty

David Zimmerman

Javier Felip Leon

Maruti Gupta Hyde

Stephen T Palermo

Mrittika Ganguli

Lokpraveen B Mosur

Chandan Egbert

Rameshkumar G Illikkal

Kenneth D Shoemaker

Ravikumar Balakrishnan

Michael A Parker

Gabriel Arrobo Vidal

Rita Chattopadhyay

Piotr Wysocki

Bassam N Coury

Kevin B Stanton

Yipeng Wang

Albert S Cheng

Anjaneya Reddy Chagam Reddy

Michael Mesnier

Udayan Mukherjee

Neelam Chandwani

Shrikant M Shah

Amin Firoozshahian

Robert J Munoz

Various systems and methods for implementing computational storage are described herein. An orchestrator system is configured to: receive, at the orchestrator system, a registration package, the registration package including function code, a logical location of input data for the function code, and an event trigger for the function code, the event trigger set to trigger in response to when the input data is modified; interface with a storage service, the storage service to monitor the logical location of the input data and notify a location service when the input data is modified; interface with the location service to obtain a physical location of the input data, the location service to resolve the physical location from the logical location of the input data; and configure the function code to execute near the input data.

Computational storage in a function-as-a-service architecture

Implementation of object versioning and consistency at scale is described. An example of a computer-readable storage medium includes instructions to receive a storage request from an object management authority to store a version of a data object at a storage appliance; generate a hash value of the data object; store the data object in a scratchpad storage; transmit a verification request for the hash value of the data object to an object versioning authority; and, upon receiving affirmative verification for the hash value, move the data object from the scratchpad storage to a media storage and transmit an acknowledgement to the object management authority.

Implementation of object versioning and consistency at scale

Systems and techniques for storage-class memory device including a network interface are described herein. A write for a network communication is received by the host interface of the memory device. Here, the network communication includes a header. The header is written to a non-volatile storage array managed by a memory controller. A network command is detected by the memory device. Here, the network command includes a pointer to the header in the non-volatile storage array. The header is retrieved from the non-volatile storage array and a packet based on the header is transmitted via a network interface of the memory controller.

Storage class memory device including a network

Methods, apparatus, systems, and articles of manufacture are disclosed for data resiliency in an edge network environment. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to at least one of execute and/or instantiate the instructions to generate spectrum metadata based on spectrum data, determine a resiliency operation based on one or more resiliency requirements, generate a resiliency policy based on at least one of the resiliency operation or the one or more resiliency requirements, generate a resiliency operation map based on at least one of the resiliency policy or first identifiers of respective workloads associated with the network environment, the first identifiers including a second identifier, and, in response to identifying a FAFO event associated with the second identifier, execute the resiliency operation based on mapping the second identifier to the resiliency operation in the resiliency operation map.

Systems, apparatus, and methods for data resiliency in an edge network environment

Systems, apparatuses, and methods provide for memory management where an infrastructure processing unit bypasses a central processing unit. Such an infrastructure processing unit determines if incoming packets of memory traffic trigger memory rules stored by the infrastructure processing unit. The incoming packets are routed to the central processing unit in a default mode when the incoming packets do not trigger the memory rules. Conversely, the incoming packets are routed to the infrastructure processing unit and bypass the central processing unit in an inline mode when the incoming packets trigger the memory rules. A memory architecture communicatively coupled to the central processing unit receives a set of atomic transactions from the infrastructure processing unit that bypasses the central processing unit and performs the set of atomic transactions from the infrastructure processing unit.

Memory schemes for infrastructure processing unit architectures

A digital twin model is generated for physical nodes of an edge network. The digital twin model includes a digital twin for a physical node of the physical nodes. An error is identified of the physical node or the digital twin for the physical node. The digital twin model is updated to halt communication with the physical node or the digital twin of the physical node. A path is created to another physical node or a digital twin of the another physical node in the digital twin model.

Digital twin framework for next generation networks

Methods, apparatus, systems, and articles of manufacture are disclosed to increase resiliency in self-healing mechanisms. At least one non-transitory machine-readable medium comprises instructions that, when executed, cause at least one processor to at least partition computational resources of a first host into a primary partition and a shadow partition, the primary partition to communicate with a second host, apply a fix for the primary partition, determine if the primary partition can communicate with the second host during the application of the fix, cause, in response to the determination that the primary partition cannot communicate with the second host during the application of the fix, the shadow partition to communicate with the second host; and transfer communication with the second host from the shadow partition to the primary partition, the transfer in response to a determination that the application of the fix is complete.

Methods and apparatus to increase resiliency in self-healing mechanisms

Various aspects of methods, systems, and use cases include security-based orchestration. A method may include evaluating, within a secure environment of an untrusted device, a preamble to determine a set of security requirements. The method may include, providing, to an attestation server, an indication of security parameters for services of the untrusted device corresponding to security requirements of the set of security requirements, and in response to receiving a confirmation from the attestation server, providing a request to the untrusted device outside the secure environment to generate a trusted domain including the services.

Network supported low latency security-based orchestration

Examples described herein relate to a system comprising at least one processor and circuitry to: determine multiple configurations of hardware resources to perform a workload associated with a workload request in a subsequent stage based on a pre-processing operation associated with the workload request and at least one service level agreement (SLA) parameter associated with the workload request. In some examples, an executable binary is associated with the workload request and execution of the executable binary performs the pre-processing operation. In some examples, the circuitry is to store the multiple configurations of hardware resources to perform a workload associated with the workload request in a subsequent stage, wherein the multiple configurations of hardware resources are available for access by one or more accelerator devices to perform the workload.

Resource selection based in part on workload

Various approaches for implementing multi-tenant data protection are described. In an edge computing system deployment, a system includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a workflow execution plan that includes workload metadata defining a plurality of workloads associated with a plurality of edge service instances executing respectively on one or more edge computing devices. The workload metadata is translated to obtain workload configuration information for the plurality of workloads. The workload configuration information identifies a plurality of memory access configurations and service authorizations identifying at least one edge service instance authorized to access one or more of the memory access configurations. The memory is partitioned into a plurality of shared memory regions using the memory access configurations. A memory access request for accessing one of the shared memory regions is processed based on the service authorizations.

Multi-tenant data protection in edge computing environments

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

Failover for pooled memory

Systems and techniques for cross-layer automated fault tracking and anomaly detection are described herein. Anomaly data may be obtained from a plurality of layers of a network. Elements of the anomaly data may be identified that correspond to a data flow of an application executing on the network. An artificial intelligence model may be trained using the elements of the anomaly data to generate an impact score for the application. The impact score may be generated for the application by evaluating current network metrics using the artificial intelligence model. An operational component of the network may be modified based on the impact score.

Cross-layer automated fault tracking and anomaly detection

A system comprising a traffic handler comprising circuitry to determine that data of a memory request is stored remotely in a memory pool; generate a packet based on the memory request; and direct the packet to a path providing a guaranteed latency for completion of the memory request.

Memory pooled time sensitive networking based architectures

Apparatus and methods for data lifecycle management in an edge environment are disclosed herein. An example apparatus includes an operation executor to identify a first operation to be performed for a data object at an edge node in an edge environment and a second operation to be performed for the data object, the first operation different that the second operation. The example apparatus includes a time parameter retriever to retrieve a first time value associated with the first operation from a data source and a second time value associated with the second operation from the data source. The operation executor is to execute the first operation in response to the first time value and to execute the second operation in response to the second time value.

Apparatus, systems, articles of manufacture, and methods for data lifecycle management in an edge environment

A computing node includes network interface circuitry and processing circuitry. The processing circuitry assigns available computing resources to a plurality of slice contexts. Each slice context of the plurality includes resource allocations of the available computing resources associated with multiple communication networks. A first portion of the resource allocations is designated as dedicated resources and a second, remaining portion is designated as shared resources. A FAFO event associated with a workload is detected. The workload executes on a network slice instance (NSI) associated with a slice context of a subset of slice contexts. The configuration of the NSI is restored to a pre-FAFO event state based on reconfiguring one or both of the dedicated resources or the shared resources of the slice context based on the resource allocations of at least a second slice context in the subset of slice contexts.

End-to-end network slicing (ENS) from ran to core network for next generation (NG) communications

Growing community of inventors

Barcelona, Spain

Francesc Guim Bernat