Intel Corporation

Other

Imtel Corporation

Francesc Guim Bernat

Kshitij Arun Doshi

Karthik Kumar

Ned M Smith

Thomas Willhalm

Suraj Prabhakaran

Mark A Schmisseur

Timothy Verrall

Susanne M Balle

Raj K Ramanujan

Kapil Sood

Rajesh Poornachandran

Sujoy Sen

Andrew J Herdrich

Rahul Khanna

S M Iftekharul Alam

Satish Chandra Jha

Christian Maciocco

John Joseph Browne

Vincent J Zimmer

Nageen Himayat

Murugasamy K Nachimuthu

Srikathyayani Srikanteswara

Mohan J Kumar

Mats Gustav Agerstam

Rita H Wouhaybi

Mark D Yarvis

Vinodh Gopal

Ravi L Sahita

Matthew James Adiletta

Robert G Blankenship

Ravishankar Iyer

Liuyang L Yang

Katalin Klara Bartfai-Walcott

Sanjay Bakshi

Vadim Sukhomlinov

Hassnaa Moustafa

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Ren Wang

Patrick L Connor

Arvind Srinivasan

Vincent R Scarlata

Alex Nayshtut

Yang-Seok Choi

Ignacio Javier Alvarez

Farid Adrangi

Pete D Vogt

Scott P Dubal

Daniel Rivas Barragan

Alexander Bachmutsky

Evan Custodio

Slawomir Putyrski

Marcos Emanuel Carranza

Brinda Ganesh

Raghu R Kondapalli

Tarun Viswanathan

Henry M Mitchel

Vesh Raj Sharma Banjade

Dario Sabella

Narayan Ranganathan

Patrick G Kutch

Paul H Dormitzer

Edwin Verplanke

Miltiadis Filippou

Lidia Warnes

Yi Zhang

Durgesh Srivastava

Ramanathan Sethuraman

Kuilin Clark Chen

Mona Vij

Dimitrios Ziakas

Nilesh K Jain

Eve M Schooler

David Israel Gonzalez Aguirre

David A Koufaty

Javier Felip Leon

David Zimmerman

Maruti Gupta Hyde

Thomas E Willis

Stephen T Palermo

Mrittika Ganguli

Lokpraveen B Mosur

Chandan Egbert

Rameshkumar G Illikkal

Kenneth D Shoemaker

Gabriel Arrobo Vidal

Michael A Parker

Robert G Southworth

Ravikumar Balakrishnan

Rita Chattopadhyay

Piotr Wysocki

Bassam N Coury

Yipeng Wang

Kevin B Stanton

Albert S Cheng

Anjaneya Reddy Chagam Reddy

Michael Mesnier

Udayan Mukherjee

Neelam Chandwani

Embodiments of apparatuses, methods, and systems for a hierarchical multi-tenant processor scheme are disclosed. In an embodiment, a processor includes circuitry to execute threads, registers to store first values to define a tenant hierarchy, registers to store second values to specify a location of a thread corresponding to a tenant within the tenant hierarchy, and circuitry to include the second values in a request to access a resource. Use of the resource is to be monitored or controlled based on the location of the tenant within the tenant hierarchy.

Global unified interdependent multi-tenant quality-of-service processor scheme

Methods, apparatus, and software for remote storage of hardware microservices hosted on other processing units (XPUs) and SOC-XPU Platforms. The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). Software, via execution on the SOC, enables the platform to pre-provision storage space on a remote storage node and assign the storage space to the platform, wherein the pre-provisioned storage space includes one or more container images to be implemented as one or more hardware (HW) microservice front-ends. The XPU/FPGA is configured to implement one or more accelerator functions used to accelerate HW microservice backend operations that are offloaded from the one or more HW microservice front-ends. The platform is also configured to pre-provision a remote storage volume containing worker node components and access and persistently store worker node components.

Remote storage for hardware microservices hosted on XPUs and SOC-XPU platforms

Systems, methods, articles of manufacture, and apparatus for end-to-end hardware tracing in an Edge network are disclosed. An example compute device includes at least one memory, instructions in the compute device, and processing circuitry to execute the instructions to, in response to receiving detecting an object having a global group identifier, generate monitoring data corresponding to a respective process executing on the compute device, the monitoring data including a process identifier, index the monitoring data having the process identifier to the corresponding global group identifier, synchronize a time stamp of the monitoring data to a network time protocol corresponding to the global group identifier, and transmit the indexed and synchronized monitoring data as tracing data in to the a tracing datastore.

Systems, methods, articles of manufacture, and apparatus for end-to-end hardware tracing in an edge network

Methods, apparatus, systems, and articles of manufacture are disclosed that reduce latency and bandwidth consumption when sharing memory across a distributed coherent Edge computing system. The distributed coherent Edge computing system disclosed herein configures a compute express link (CXL) endpoint to share data between memories across an Edge platform. The CXL endpoint configures coherent memory domain(s) of memory addresses, which are initialized from an Edge device connected to the Edge platform. The CXL endpoint also configures coherency rule(s) for the coherent memory domain(s). The CXL endpoint is implemented to snoop the Edge platform in response to read and write requests from the Edge device. The CXL endpoint selectively snoops memory addresses within the coherent memory domain(s) that are defined as coherent based on the coherency rule(s).

Methods and apparatus to share memory across distributed coherent edge computing system

A network switch includes a memory device to store a stream information of a plurality of data streams being handled by the network switch, the stream information including a stream identifier, a stream service level agreement (SLA), and a stream traffic type; accelerator circuitry to apply stream transformation functions to data streams; telemetry circuitry to monitor egress ports of the network switch; and scheduler circuitry to: receive telemetry data from the telemetry circuitry to determine that a utilization of egress ports of the network switch is over a threshold utilization; determine a selected data stream of the plurality of data streams to transform; use the accelerator circuitry to transform the selected data stream to produce a transformed data stream, wherein the transformed data stream complies with a corresponding stream SLA; and transmit the transformed data stream on an egress port.

Switch-based adaptive transformation for edge appliances

Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

Techniques for artificial intelligence capabilities at a network device

Various systems and methods for implementing computational storage are described herein. An orchestrator system is configured to: receive, at the orchestrator system, a registration package, the registration package including function code, a logical location of input data for the function code, and an event trigger for the function code, the event trigger set to trigger in response to when the input data is modified; interface with a storage service, the storage service to monitor the logical location of the input data and notify a location service when the input data is modified; interface with the location service to obtain a physical location of the input data, the location service to resolve the physical location from the logical location of the input data; and configure the function code to execute near the input data.

Computational storage in a function-as-a-service architecture

Implementation of object versioning and consistency at scale is described. An example of a computer-readable storage medium includes instructions to receive a storage request from an object management authority to store a version of a data object at a storage appliance; generate a hash value of the data object; store the data object in a scratchpad storage; transmit a verification request for the hash value of the data object to an object versioning authority; and, upon receiving affirmative verification for the hash value, move the data object from the scratchpad storage to a media storage and transmit an acknowledgement to the object management authority.

Implementation of object versioning and consistency at scale

Systems and techniques for storage-class memory device including a network interface are described herein. A write for a network communication is received by the host interface of the memory device. Here, the network communication includes a header. The header is written to a non-volatile storage array managed by a memory controller. A network command is detected by the memory device. Here, the network command includes a pointer to the header in the non-volatile storage array. The header is retrieved from the non-volatile storage array and a packet based on the header is transmitted via a network interface of the memory controller.

Storage class memory device including a network

Methods, apparatus, systems, and articles of manufacture are disclosed for data resiliency in an edge network environment. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to at least one of execute and/or instantiate the instructions to generate spectrum metadata based on spectrum data, determine a resiliency operation based on one or more resiliency requirements, generate a resiliency policy based on at least one of the resiliency operation or the one or more resiliency requirements, generate a resiliency operation map based on at least one of the resiliency policy or first identifiers of respective workloads associated with the network environment, the first identifiers including a second identifier, and, in response to identifying a FAFO event associated with the second identifier, execute the resiliency operation based on mapping the second identifier to the resiliency operation in the resiliency operation map.

Systems, apparatus, and methods for data resiliency in an edge network environment

Systems, apparatuses, and methods provide for memory management where an infrastructure processing unit bypasses a central processing unit. Such an infrastructure processing unit determines if incoming packets of memory traffic trigger memory rules stored by the infrastructure processing unit. The incoming packets are routed to the central processing unit in a default mode when the incoming packets do not trigger the memory rules. Conversely, the incoming packets are routed to the infrastructure processing unit and bypass the central processing unit in an inline mode when the incoming packets trigger the memory rules. A memory architecture communicatively coupled to the central processing unit receives a set of atomic transactions from the infrastructure processing unit that bypasses the central processing unit and performs the set of atomic transactions from the infrastructure processing unit.

Memory schemes for infrastructure processing unit architectures

A digital twin model is generated for physical nodes of an edge network. The digital twin model includes a digital twin for a physical node of the physical nodes. An error is identified of the physical node or the digital twin for the physical node. The digital twin model is updated to halt communication with the physical node or the digital twin of the physical node. A path is created to another physical node or a digital twin of the another physical node in the digital twin model.

Digital twin framework for next generation networks

Methods, apparatus, systems, and articles of manufacture are disclosed to increase resiliency in self-healing mechanisms. At least one non-transitory machine-readable medium comprises instructions that, when executed, cause at least one processor to at least partition computational resources of a first host into a primary partition and a shadow partition, the primary partition to communicate with a second host, apply a fix for the primary partition, determine if the primary partition can communicate with the second host during the application of the fix, cause, in response to the determination that the primary partition cannot communicate with the second host during the application of the fix, the shadow partition to communicate with the second host; and transfer communication with the second host from the shadow partition to the primary partition, the transfer in response to a determination that the application of the fix is complete.

Methods and apparatus to increase resiliency in self-healing mechanisms

Various aspects of methods, systems, and use cases include security-based orchestration. A method may include evaluating, within a secure environment of an untrusted device, a preamble to determine a set of security requirements. The method may include, providing, to an attestation server, an indication of security parameters for services of the untrusted device corresponding to security requirements of the set of security requirements, and in response to receiving a confirmation from the attestation server, providing a request to the untrusted device outside the secure environment to generate a trusted domain including the services.

Network supported low latency security-based orchestration

Examples described herein relate to a system comprising at least one processor and circuitry to: determine multiple configurations of hardware resources to perform a workload associated with a workload request in a subsequent stage based on a pre-processing operation associated with the workload request and at least one service level agreement (SLA) parameter associated with the workload request. In some examples, an executable binary is associated with the workload request and execution of the executable binary performs the pre-processing operation. In some examples, the circuitry is to store the multiple configurations of hardware resources to perform a workload associated with the workload request in a subsequent stage, wherein the multiple configurations of hardware resources are available for access by one or more accelerator devices to perform the workload.

Resource selection based in part on workload

Growing community of inventors

Barcelona, Spain

Francesc Guim Bernat