Taiwan Semiconductor Manufacturing Comp. Ltd.

Fouriers Tseng

Chin-Kai Liu

Peng-Cheng Chou

Huey Ling Chen

Pin Hsiang Chin

At Chuan Chen

Thomas Hung

Mei Fun Chen

The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by first alternatingly depositing layers of BPTEOS oxide and PETEOS oxide onto a semiconductor substrate and then forming a contact hole through the insulating layers utilizing a wet etchant that has high selectivity for the PETEOS oxide layers such that a zig-zag surface is formed in the contact hole and subsequently a capacitor that has improved charge storage capacity. The present invention novel method can be used to form any type of stacked capacitors, for instance, a stacked capacitor, a fin-type stacked capacitor, a crown-type stacked capacitor, etc.

Method for fabricating a DRAM capacitor and device made

An integrated circuit debugging system is provided for debugging the integrated circuits with bi-directional terminals is disclosed. The system includes clock unit for providing clocks, and address generating unit for generating address responsive to the provided clock. An I/O control memory is used to store pin status of an integrated circuit under test corresponding to each of the generated address; and a timing diagram memory is used to store fitting value of the integrated circuit. Moreover, the system includes an I/O manipulating unit for directing signal into and out of the integrated circuit according to the stored pin status of the I/O control memory, and for comparing the signal out of the integrated circuit under test and the fitting value from the timing diagram memory. Further, feedback control unit is configured to control the address generation of the address generating unit.

Integrated circuit debugging system

An universal ball grid array (BGA) test board for performing a failure analysis on any size IC chips and a method for performing such analysis are disclosed. In the universal BGA test board, an electrically insulating material is used as a substrate with a rectangular opening provided at a center. A plurality of spaced-apart conductive lines are provided surrounding and adjacent to the center opening for use as ground and power supply respectively. A multiplicity of conductive leads, a multiplicity of ball pads are then provided on the surface of the substrate with a multiplicity of conductive traces connecting thereinbetween such that one conductive lead is connected to one ball pad. The test method can be easily conducted by first wire bonding the conductive leads to the bond pads on the IC chip and then contacting the ball pads with probe needles for feeding in test signals into the IC chip. Defects are shown as hot spots in a liquid crystal material that is coated on the top surface of the IC chip.

Universal BGA board for failure analysis and method of using

A method for conducting backside failure analysis on a wafer that only requires simple bias conditions to be fed into defective IC dies and a wafer test specimen which enables such test are disclosed. In the method, a wafer can be first provided that contains at least one defective IC die in an active (or front) surface, at least two conductive metal strips formed of a metal foil are then adhesively bonded to the active surface of the wafer juxtaposed to the at least one defective IC die. At least two lead wires are then bonded by a wire bonding technique between the at least two conductive metal strips and at least two bond pads on the defective IC die for establishing electrical communication therein between. A bias voltage such as a VCC signal or a clock signal can then be fed to the defective IC die through the at least two conductive metal strips, while the defect being observed from the backside of the wafer with an optical detector. The present invention novel method and the wafer test specimen enable the method to be executed at a relatively low cost and a shortened analysis time since a complete wafer can be tested without first been severed and packaged into IC chips as normally required in conventional test methods. Furthermore, the present invention novel test method can be executed on selected defective IC dies on a wafer without disturbing, or damaging other good dies.

Method for backside failure analysis requiring simple bias conditions

A method for conducting a backside failure analysis on a ball grid array (BGA) package that does not require a chemical etching step is described. In the method, a substrate can first be removed mechanically from the BGA package to expose a plastic encapsulated IC chip. The molding compound on the backside of the IC chip can then be removed by a mechanical method such as polishing or preferably, chemical mechanical polishing. Simultaneously with the exposure of the backside of the IC chip, the ends of a plurality of bonding wires which are connected to the bond pads on the top surface of the IC chip is also exposed. A plurality of probe needles or a bonder can then be used to make electrical contact with the ends of the bonding wires such that signals may be fed into the IC chip for conducting a failure analysis. The present invention novel method provides the advantage that the observation for the failure sites and the electrical connections to the IC chip can all be conducted on the same surface of the package and thus be carried out at low cost and in a simplified manner.

Backside failure analysis for BGA package

A method/system is provided for performing a design review checking operation and analyzing the resultant data. Perform a DRC operation describing chip features and generating flags for violation sites including patterns and paths. Execute pattern analysis and grade classification steps for the violation sites. Generate a vector array for each chip feature for each of the violation sites. Compare the vector arrays to determine whether degrees of similarity of geometries of chip features of violation sites meet one of a set of criteria. Classify the violation sites into classes with similar criteria. Select representative arrays from each class of violation sites to provide an output. Calculate distance from a violation site from the origin in a two-dimensional array. Give a grade to each vector array to indicate the level of seriousness of the rule violation by the site. Use a layout viewer to view the error flags generated by pattern analysis and grade classification steps.

Efficient design rule check (DRC) review system

An improved method for sectioning a semiconductor wafer using a focused ion beam (FIB) apparatus permits a clearer image of the site of the cut to be formed from secondary electrons produced by the beam. The clearer image helps the operator of the FIB apparatus to make a more accurate cut. Before the FIB cut is made, a laser is used to cut into the wafer to expose the lowermost layer of silicon dioxide. This oxide and any oxide splatters from the laser cut are then removed with an oxide etcher. The FIB cut can then be made without splattering silicon dioxide over the area being viewed. A low beam current is used for the FIB cut.

Method for sectioning a semiconductor wafer with FIB for viewing with SEM

A new method of forming an amorphous silicon glue layer in the formation of a contact is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. An amorphous silicon layer is deposited overlying the insulating layer and within the opening. Ions are implanted into the amorphous silicon layer whereby grain sizes within the amorphous silicon layer are reduced. Native oxide on the surface of the amorphous silicon layer is removed. A titanium/titanium nitride layer is deposited overlying the amorphous silicon layer. A metal layer is deposited overlying the titanium/titanium nitride layer and filling the opening. The substrate is annealed whereby the titanium layer reacts with the amorphous silicon layer and the silicon semiconductor substrate to form titanium silicide. The metal layer is etched back or patterned to complete metallization in the fabrication of an integrated circuit device.

Growing community of inventors

Hsin-Chu, Taiwan

Fouriers Tseng