Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Forrest M Phillips

Thomas F Joyce

Ming T Miu

Jian-Kuo Shen

Richard P Kelly

David E Cushing

Ralph M Lombardo, Jr

Robert V Ledoux

A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged. Using this information circuits in the bus interface interrupt arrangement are operated to pass data and addresses between the primary bus and the chosen bus. These circuits are operated in a manner to pass data between busses having different data path sizes.

Bus interface interrupt apparatus

A virtual memory management cache memory system has a plurality of directory and buffer store levels for storing page descriptor information. The cache memory directories and a least recently used (LRU) apparatus for replacing information within the buffer store on a least recently used basis are constructed from the same type of standard cache address directory part. Programmable control circuits generate the required input data and control signals which are applied to the LRU apparatus for obtaining signals which indicate a next level to be replaced on a least recently used basis and for updating the contents of the LRU apparatus on a most recently used basis.

Least recently used replacement level generating apparatus and method

During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.

Ring reduction logic using parallel determination of ring numbers in a

In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.

Apparatus and method for address translation of non-aligned double word

A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

Virtual cache system using page level number generating CAM to access

A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal. The contents of the output register stage accurately and instantaneously defines the least recently used replacement level for use by a cache memory.

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North Chelmsford, MA, United States of America

Forrest M Phillips