International Business Machines Corporation

Forrest Lee Wade

Brent Cameron Beardsley

Carl Evan Jones

Gary William Batchelor

Michael T Benhase

Robert Earl Medlin

Dell Patrick Leabo

Matthew J Kalos

Adalberto Guillermo Yanes

Stephen Gouze Luning

Shanker Singh

Juan Antonio Yanes

Donald J Lang

Mark C Johnson

Joe-Ming Cheng

Russell Lee Ellison

Marc Ethan Goldfeder

Sudha Sarma

Brandt C Centerwall

Belayneh Tafesse

Robert L Berry

Disclosed is a bridge system and method for prefetching data to return to a read request from an agent. The bridge system includes at least one memory device including a counter indicating a number of prefetch operations to perform to prefetch all the requested data, a first buffer capable of storing prefetch requests, and a second buffer capable of storing read data. Control logic implemented in the bridge system includes means for queuing at least one prefetch operation in the first buffer while the counter is greater than zero. The control logic then executes a queued prefetch operation, subsequently receives the prefetched data, and stores the prefetched data in the second buffer. The stored prefetched data is returned to the requesting agent.

Method and system for perfetching data in a bridge system

Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

Method and system for multiple read/write transactions across a bridge system

Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent. In a similar manner, in delayed write operations, the write data may also be gathered from several write operations and assembled into an address boundary-aligned block of write data before the bridge circuit forwards the write data to the target device.

Method and system for gathering and buffering sequential data for a transaction comprising multiple data access requests

Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Data caching with a partially compressed cache

Disclosed is a bridge system for processing read transactions over a bus in which in a preferred embodiment prefetched data stored in a buffer is not discarded if the address of the requested read does not match the beginning address of the prefetched data. Instead, the bridge system skips to the next address of the prefetched data stored in the buffer and compares that address to the address of the read request to determine if a match exists. If the requested read address does match the next prefetched data address, the prefetched data starting at that next address is read out and forwarded to the requesting agent. Alternatively, if there is not a match, the bridge skips again to the next address and continues checking for a match until either the prefetched data is exhausted or another predetermined limit has been reached. In this manner, many unnecessary data reads of data already prefetched in the buffer may be avoided.

Method and system for reading prefetched data across a bridge system

Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.

Bridge failover system

A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up. The NV-Buffer is a fast drain buffer and is equipped with a backup power source sufficient to hold up a power needed to transfer the data when the power is down.

Secure store implementation on common platform storage subsystem (CPSS)

A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have. If desired, an additional, user-selectable supplementary delay unit may be used to increase the delay provided by the delay module, thereby increasing or offsetting the delay of the selected sampling clock signal. The delay module provides a delayed clock signal to synchronize receipt of Read data signals from the memory bank at a clocked latch, enabling the latch to receive the Read data signals during the appropriate data valid window. Specifically, the latch is activated by receipt of Read command signals, which may be coordinated, for example, with the rising edge of the delayed clock signal. The latched Read data signals are then available for use by other logic circuitry.

Memory controller for reading data from synchronous RAM

A systematic method for detecting which head in a multiple head storage device contains errors and may be misaligned, and correcting for misalignment so that the data can be recovered. The apparatus includes a data buffer for storing a block of interleaved data read from the multiple head storage device, status bits, error detection circuitry for determining from the interleaved data, which if any of the heads is misaligned and for setting the status bits, data recovery control logic responsive to the status bits for sending control signals to the multiple head storage device for causing the misaligned head to move its position by small increments and to read data until the status bits indicate that the misaligned head has become aligned, and circuitry responsive to the status bits for writing data from the newly realigned head over the data which was read when that head was misaligned. The method includes steps of reading a block of interleaved data from a multiple head storage device and sending that data to a data buffer; detecting the existence of a misaligned head in determining which head is misaligned; generating error detection signals which indicate which head is misaligned; setting status bits in response to the error detection signals and sending control signals to the multiple head storage device to move the misaligned head by small increments and to read data from the misaligned head. The steps are repeated until the status bits indicate that the misaligned head has become realigned. After the head has become realigned the data which was stored in the storage buffer when the head was misaligned is written over by data read from the newly aligned head.

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Tucson, AZ, United States of America

Forrest Lee Wade