National Semiconductor Corporation

Forrest E Norrod

Willard S Briggs

Brian Dennis Falardeau

Christopher G Wilcox

Christopher M Herring

Sameer Y Nanavati

A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.

Data transfer with highly granular cacheability control between memory and a scratchpad area

A highly integrated central processing unit employs a single external physical bus having first and second protocols to support an L2 cache and a general purpose peripheral interface respectively, to avoid bond-out of the CPU bus to the external world and to steal unused bandwidth for L2 cache accesses while maintaining a standard peripheral bus interface.

Interfacing an L2 cache to a single bus having alternative protocols

A processing system includes a graphics subsystem that directly renders raster data to system memory and moves bitmaps between locations within system memory with the graphics subsystem providing the data and a processor providing the virtual-to-physical addresses with privilege and protection check mechanisms.

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Boulder, CO, United States of America

Forrest E Norrod