Altera Corporation

Foong Tek Chan

Ket Chiew Sia

Chiakang Sung

Khai Nguyen

Boon Jin Ang

Xiabao Wang

A high speed IO buffer is disclosed. The high speed IO buffer includes a first P-type metal oxide semiconductor (PMOS) transistor coupled to an IO voltage source. The high speed IO buffer also includes a first N-type metal oxide semiconductor (NMOS) transistor coupled to a ground source, a second PMOS transistor coupled to the first PMOS transistor and a pad and a second NMOS transistor coupled to the first NMOS transistor and the pad. The first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are arranged in a cascoded arrangement.

High speed IO buffer

Methods, circuits, and systems for termination calibration are provided. Differential input buffer circuitry is used to compare a signal level at an input/output pad and a first reference signal level. Control circuitry is used to control a controllably variable impedance based on the output of the differential input buffer circuitry. Optionally, second differential input buffer circuitry is used to compare the signal level at the input/output pad to a second reference signal level. The control circuitry is used to control the controllably variable impedance based on the output of both the first and the second differential input buffer circuitry.

Growing community of inventors

Kuala Lumpur, Malaysia

Foong Tek Chan