Taiwan Semiconductor Manufacturing Comp. Ltd.

Synopsys, Inc.

Synopsys Taiwan Co., Ltd.

Springsoft, Inc.

Springsoft Usa, Inc.

Fong-Yuan Chang

Po-Hsiang Huang

Sheng-Hsiung Chen

Yi-Kan Cheng

Lee-Chung Lu

Chun-Chen Chen

Li-Chun Tien

Chin-Chou Liu

Shao-Huan Wang

Chung-Hsing Wang

Ka Fai Chang

Chung-Te Lin

Cheng-Hung Yeh

Kuo-Nan Yang

Hui Yu Lee

Ting Yu Chen

Hiranmay Biswas

Yen-Pin Chen

Wai-Kei Mak

Ren-Song Tsay

Tzu-Hen Lin

Tai-Yu Cheng

Wei-Shun Chuang

Aftab Alam Khan

Sheng-Fong Chen

Hsian-Ho Chang

Ruey-Shi Rau

Shih-Lien Linus Lu

Yi-Chun Shih

Jerry Chang-Jui Kao

Yi-Shin Chu

Chin-Her Chien

Ho Che Yu

Jyun-Hao Chang

XinYong Wang

Tung-Chieh Chen

Chin-chou Liu

Tsui-Ping Wang

Ting-Wei Chiang

Jerry Chang Jui Kao

Ya-Chi Chou

Shun-Li Chen

Chung-hsing Wang

Sheng-hsiung Chen

Jung-Chou Tsai

Chih-Liang Chen

Shun Li Chen

Po-Yu Chen

Chih-wei Chang

Pochun Wang

Hsin-Po Wang

Chien-Ying Chen

Kai-Ming Liu

Jyh Chwen Frank Lee

Chin-Yuan Huang

Kai-Yun Lin

Cheng-Yu Lin

Ching-Yi Lin

Jeo-Yen Lee

Yao-Hsien Tsai

Yu-Sheng Lu

Sung-Han Tsai

Tai-Yu Wang

Ming-Ke Tsai

Yi-Der Lin

Ru Lin Yang

Chun-Cheng Chi

Hsueh Liang Hsu

A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

SOIC chip architecture

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Layout design for header cell in 3D integrated circuits

A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Systems and methods of estimating thermal properties of semiconductor devices

A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit

A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Memory device having bitline segmented into bitline segments and related method for operating memory device

An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Integrated circuit having a high cell density

A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

Method and system of forming integrated circuit

An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mrow extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mrow are grouped into a first group, a second group and an ngroup extending along the second direction. The second pads in each of the first row, the second row and the mrow are grouped into a first group, a second group and an ngroup extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nconductive lines.

Interconnect structure and method for forming the same

An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.

Integrated circuit and method of generating integrated circuit layout

Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Standard cells and variations thereof within a standard cell library

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

Electromagnetic shielding metal-insulator-metal capacitor structure

Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

Integrated circuit and layout method for standard cell structures

A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

Growing community of inventors

Hsinchu County, Taiwan

Fong-Yuan Chang