Intel Corporation

Fong-Shek Lam

Paul S Diefenbaugh

Jason Daniel Tanner

Michael N Derr

Arthur Jeremy Runyan

Kim A Meinerth

Prashant D Chaudhari

Prasanna C Shah

Jerry A Verseput

Sameer Kalathil Perazhi

Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

Video bandwidth optimization for multi-monitor systems

An overlay video processing system provides an early start to pixel processing for the next overlay scan line. The overlay processor begins processing the next overlay scan line while still displaying the current scan line. A FIFO buffer is used to provide the overlay video data to the display. When the buffer provides a predetermined amount of data to the current overlay scan line, the buffer begins to load the data for the next overlay scan line. In one embodiment, the buffer may begin loading data for the next overlay scan line when approximately half the current overlay scan line is displayed.

Overlay scan line processing

A method and apparatus of defining a line buffer configuration in a memory is disclosed. In one embodiment, the method and apparatus receives input data information and mode information, proceeds to select a type of the line buffer configuration according to the mode information, and dynamically generates addresses for the selected type of line buffer configuration in the memory according to the input data information.

Method and apparatus for dynamically defining line buffer configurations

A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state. Next, detect that the PC card has been completely inserted or removed by monitoring the ground pins or the card detect signal pins. Next, apply power to the PCMCIA card socket. After a delay return the common address, data and control lines to their normal operating impedance level.

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Folsom, CA, United States of America

Fong-Shek Lam