Silicon Storage Technology, Inc.

Smart Modular Technologies, Inc.

Fong-Long Lin

Shu-Cheng Lin

Bing Yeh

Siamak Arya

Eugene Feng

Satyanarayan Shivkumar Iyer

Juei-Chi Hsu

Michael Rubino

Kwang Jin Gooi

Kangping Zhang

William Lau

Jeremy Wang

Wei Xu

Xiangyang Teng

Chi-Chung Yin

A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.

Solid state storage system with latency management mechanism and method of operation thereof

A data storage system, and a method of operation thereof, includes: a host initialization module for initializing a data storage unit; a command process module, coupled to the host initialization module, for processing a read command or a write command performed on the data storage unit; and a status scheduler module, coupled to the command process module, for generating a check status request to inquire a storage unit status of the data storage unit, wherein the check status request occurs without interrupting a host.

Data storage system with information exchange mechanism and method of operation thereof

Approaches, techniques, and mechanisms are disclosed for manufacturing and operating portable module systems. The portable module systems can provide additional computing, memory, communication, networking, and power functionality in compact package that can be connected to a host system. The portable module system can dissipate thermal energy using an embedded cooling system to allow the use of high performance components. The portable module system can improve the functionality and computing capacity of the host system by linking off the shelf component boards with the external bus using a bridge interface unit to transfer information from an internal bus to the external bus.

Portable module system

In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: 'second plurality'). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Method of testing an integrated circuit die, and an integrated circuit die

A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

Memory device having read cache

A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

Hard disk drive cache memory and playback device

A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

Motherboard having a non-volatile memory which is reprogrammable through a video display port

A single integrated circuit microcontrollerincluding embedded erasable/programmable non-volatile memoryhaving a read protection. Microcontrollercan operate within a special mode in which external circuits may access memoryby use of input/output pins. When microcontrolleractivates this special mode, a read protection flagwithin memoryis checked. The read protection flagmay be set during production of the microcontrollerafter instructional data or firmware has been installed onto memory. If the read protection flaghas been set, the contents of memoryare erased or reprogrammed prior to allowing access to memory. In this manner, external circuits cannot access instructional data or firmware that is stored in memory

Microcontroller having embedded non-volatile memory with read protection

A single integrated circuit microcontrollerincludes an embedded erasable/programmable non-volatile memoryhaving a read protection capability. Microcontrollercan operate within a special mode in which external circuits may access memoryby use of input/output pins. When microcontrolleractivates this special mode, a read protection flagwithin memoryis checked. The read protection flagmay be set during production of the microcontrollerafter instructional data or firmware has been installed onto memory. If the read protection flaghas been set, only certain portions of the memorymay be read, depending upon the value of the read protection flag

Microcontroller having an embedded non-volatile memory array with read protection for the array or portions thereof

A solid state peripheral storage device has a mapping memory which receives a first address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units and the mapping memory unit are all made out of solid state floating gate storage cells. Through the use of the mapping memory, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, in the event a portion of the mapping memory unit becomes defective, the mapping unit is then mapped by an indirect address to a different location in the memory unit where the mapping of the first address to PSN address is stored.

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Fremont, CA, United States of America

Fong-Long Lin