Infineon Technologies Ag

Fong Lim

Ralf Otremba

Josef Hoeglauer

Xaver Schloegel

Juergen Schredl

Michael Stadler

Chooi Mei Chong

Abdul Rahman Mohamed

Paul Armand Asentista Calo

Yang Hong Heng

Chee Soon Law

Zakaria Abdullah

Mei Qi Tay

Ser Yee Keh

See Yau Lee

Tien Heng Lem

Tek Keong Gan

Ida Fischbach

An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.

Electrical interconnect structure with radial spokes for improved solder void control

A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.

Semiconductor device using diffusion soldering

A semiconductor chip assembly includes a semiconductor chip and a pyrolytic graphite element that is an electrode that is electrically connected to and provides electrical conduction of current from the chip during operation of the chip.

Semiconductor chip assembly

A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a ribbon. The ribbon includes a first metal layer and a second metal layer. The first metal layer is welded to the first chip and the second metal layer is attached to the second chip.

Semiconductor package with ribbon with metal layers

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Melaka, Malaysia

Fong Lim