Siemens Aktiengesellschaft

Focko Frieling

Ewald Michael

Wolfgang Nikutta

A signal-level converter for controlling digital MOS circuits, particularly an address-buffer circuit for dynamic MOS memories, is designed in integrable form in MOS technology and is addressed on one hand by a first supply potential and a second supply potential connected as the reference potential, and on the other hand, at a signal input by the digital control signal to be processed, and furthermore includes cross-coupled field-effect transistor pairs as well as two output terminals carrying signals inverted relative to each other for controlling the digital circuit.

Signal-level converter

Integrated pulse former constructed in MIS circuit technology and connected to a first supply potential as well as to a second supply potential serving as a reference potential, and acted upon by control pulses from a pulse generator, which includes a first former part and a second former part directly addressed by the control pulses from the pulse generator, the first former part being connected to both the first and the second supply potentials and having three signal outputs, the second former part being additionally controlled via the three signal outputs of the first former part and being connected only to the first one of the two supply potentials, a first one of the signal outputs connected to and controlling a gate of a first field-effect transistor having a source-chain path directly connected, on one hand, to an output of the pulse generator furnishing the control pulses and, on the other hand, to a signal output of the second former part for furnishing secondary pulses, a second one of the three signal outputs of the first former part being connected to and controlling a gate of a second field-effect transistor having a source-drain path connecting the signal output of the second former part to one terminal of a capacitor having another terminal connected to the third one of the three signal outputs of the first former part, the one terminal of the capacitor connected to the second field-effect transistor being also connected via a third field-effect transistor to the first supply potential, the third field-effect transistor having a gate controllable, respectively, by the first supply potential and by pre-charging pulses applied to the first former part for controlling the first former part; and means provided for effecting a return of the first, second and third potentials at the respective signal outputs of the first former part to a state prevailing before onset of a final control pulse, after the end of the falling edge of the control pulses from the pulse generator and before onset of the rising edge of the next control pulse.

Circuit for generating rapid pulses

Integrated digital MOS-semiconductor circuit, including a first circuit part for generating charging and switching pulses, a second circuit part having an input connected to the first circuit part for being addressed by the pulses supplied by the first circuit part, first, second and third self-locking MOS-field effect transistors each having a source, a drain and a gate electrode, first and second capacitors having first and second terminals, the first terminal of the first capacitor being connected through the first transistor to the input of the second circuit part, the first terminal of the second capacitor being connected through the second transistor to the input of the second circuit part, a first supply potential source at reference potential, a second supply potential source different from reference potential being connected to at least one terminal of the third transistor and through the third transistor to the first terminal of the second capacitor, the second supply potential source also being connected to the gate electrode of the first transistor, the gate of the second transistor being connected between the first transistor and the first terminal of the first capacitor, means for supplying a first digital pulse having a given beginning and end to the second terminal of the first capacitor, and means for supplying a second digital pulse having a given beginning and end to the second terminal of the second capacitor, the first and second digital pulse simultaneously ending with the pulse supplied by the first circuit part, the beginning of the pulse supplied by the first circuit part occurring earlier than the beginning of the first and second digital pulses, and the beginning of the second digital pulse occurring at least as late as the beginning of the first digital pulse.

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Munich, Germany

Focko Frieling