Apple Inc.

Stats Chippac Pte. Ltd.

Chippac, Inc.

Adeia Semiconductor Bonding Technologies Inc.

Jcet Semiconductor (shaoxing) Co., Ltd.

Flynn P Carson

Marcos Karnezos

Meng Chi Lee

Jun Chung Hsu

Shakti Singh Chauhan

SeongMin Lee

Jun Zhai

Jong-Woo Ha

BumJoon Hong

Taekeun Lee

Tha-An Lin

Youngcheol Kim

Karthik Shanmugam

Raymundo M Camenforte

Harry Chandra

Il Kwon Shim

Reza A Pagaila

Kunzhong Hu

Kwan-Yu Lai

Seung Uk Yoon

Scott D Morrison

Menglu Li

Zigmund Ramirez Camacho

Seng Guan Chow

Thomas H DiStefano

David A Pakula

Rajendra D Pendse

Daniel William Jarvis

Henry Descalzo Bathan

Ian A Spraggs

Emmanuel Espiritu

In Sang Yoon

Gregory N Stephens

Dennis R Pyper

JoHyun Bae

Amir Salehi

Nathan J Bohney

Derek J Walters

Alex J Crumlin

Michael Victor Yeh

SeongHun Mun

Jonathan C Wilson

Angelo V Marasco

Kiranjit Dhaliwal

Corey S Provencher

Vu Thanh Vo

Sidharth S Dalmia

Scott L Gooch

Laura Mayer

Kumar Nagarajan

Rakshit Agrawal

Insang Yoon

Shatki S Chauhan

Koo H Lee

Ki T Ryu

Sang D Lee

Wansuk Yun

John M McCambridge

Antonio Manenti

A radio frequency package includes a first portion of an antenna array module, a second portion of the antenna array module, and a flexible cable. The first portion of the antenna array module provides a first wireless communication functionality and the second portion of the antenna array module provides a second wireless communication functionality. The flexible cable includes first surface directly coupled to the first portion of the antenna array module. The flexible cable also includes a second surface directly coupled to the second portion of the antenna array module. The flexible cable communicates signals between the first portion of the distributed antenna array module and the second portion of the antenna array module.

System packaging for millimeter wave antennas

Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.

Molded silicon on passive package

Battery systems according to embodiments of the present technology may include a battery cell having an electrode tab extending from an edge of the battery cell. The systems may also include a module electrically coupled with the battery cell. The module may be characterized by a first surface, a height, and a second surface opposite the first surface. A conductive tab coupled along the first surface of the module may extend from a first end parallel to a plane of the first surface. The conductive tab may be characterized by a curvature proximate a midpoint of the conductive tab. A distal region of the conductive tab may return back across the first surface of the module substantially parallel to the first surface. A distal portion of the electrode tab may be fixedly coupled with the distal region of the conductive tab.

Cell packaging techniques

Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

Flexible package architecture concept in fanout

Wafer level passive array packages and modules are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.

Wafer-level passive array packaging

Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

Substrate-less integrated components

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.

Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die

The present disclosure is related to printed circuit board packages and methods of assembly that may be used in the fabrication of electrical devices. Printed circuit board packages may be manufactured by stacking printed circuit board assemblies. Each printed circuit board assembly may have multiple printed circuit boards supported by a resin mold. The printed circuit board assemblies may be shaped to improve space utilization efficiency and to accommodate large electrical components that are attached to the printed circuit board package.

Stacked printed circuit board packages

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

Vertical interconnects for self shielded system in package (SiP) modules

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Self shielded system in package (SiP) modules

Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a 'known good' substrate on a support substrate.

Carrier ultra thin substrate

Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 &#x3bc;m thick.

Dual molded stack TSV package

Growing community of inventors

Redwood City, CA, United States of America

Flynn P Carson