Apple Inc.

Advanced Micro Devices Corporation

Floyd L Dankert

Jay B Fletcher

Sanjay Pant

Nathan F Hanagami

Dingkun Du

Jitendra K Agrawal

Alexander W Schaefer

Ludmil N Nikolov

Amy M Novak

Shawn Searles

Scott C Johnson

Jerry D Moench

Alberto Alessandro Angelo Puggelli

Michael B Nussbaum

Talbott Mead Houk

Joel Thornton Irby

Grady L Giles

Michael K Ciraula

Hubert Attah

Siarhei Meliukh

Nikola Jovanovic

Wenxun Huang

Di Zhao

Victor F Andrade

Enrico Zanetti

Alessandro Molari

Jianbao Wang

Kiranjit Dhaliwal

Ruopeng Wang

Gregory A Constant

Hartmut Sturm

Ofir Gilad

Seyedeh Maryam Mortazavi Zanjani

Tristan R Hudson

Randal L Posey

Michael C Braganza

John J Sullivan

Nicola Florio

Chad L Olson

Soolin Kao Chrudimsky

Jan Michael Huber

David R Reebel

Georg Diebel

Maryam Mortazavi

Jonathan A Dutra

The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

Wakeup circuit

Systems and methods described herein correspond to supply harvesting operations. Power management circuitry may receive a supply voltage from other power management circuitry. This supply voltage may be a harvested supply from the other power management circuitry. Moreover, some of the power management circuitry may be operated as controller power management circuitry to supply the supply voltage via one or more rails and some of the power management circuitry may be operated as leaf power management circuitry to harvest the supply voltage from the one or more rails. Leaf power management circuitry may exclude a regulator, enabling that leaf power management circuitry to be entered into a lower power mode than previously enabled when the regulator was included.

General purpose input/output (GPIO) supply harvesting

A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor is configured to regulate a voltage level of a power supply node using a particular one of multiple available operating modes. In response to receiving a command to reduce the voltage level of the power supply node, the power converter circuit begins to reduce the voltage level of the power supply node, while autonomously selecting different ones of available operating modes. The power converter circuit may compare to the voltage level of the power supply node to boundary levels and select a different operating mode when the voltage level of the power supply node exceeds one of the boundaries. By switching operating modes during the negative slew of the voltage level of the power supply node, the power converter may maintain a target efficiency during the reduction in voltage.

Negative slew rate control for power converters

A voltage regulator circuit included in a computer system may include multiple devices and a switch node coupled to a regulated power supply node via an inductor. The voltage regulator circuit may charge a capacitor using an input power supply signal, and couple the capacitor to the switch node using respective subsets of the multiple devices, which are selected based on one or more control signals. A control circuit may generate the one or more control signals based on a particular switching sequence, which is selected based on a ratio of a voltage level of the regulated power supply node and a voltage level input power supply signal.

Cycle transitions for buck converter circuits

A voltage regulator circuit included in a computer system may include multiple devices and a switch node coupled to a regulated power supply node via an inductor. The voltage regulator circuit may, using different subsets of the multiple devices, charge a capacitor for a first period of time and then couple the switch node to the capacitor for a second period of time. A control circuit may sense, using a common circuit, different characteristics of a current through the inductor during respective operation modes, and adjust the first and second periods of time based on the different characteristics of the current and a current operation mode.

Sense circuit for buck converter circuit

An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.

Apparatus for testing embedded memory read paths

A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Memory array with global bitline domino read/write scheme

A memory circuit. In one embodiment, the memory circuit includes a first one-hot multiplexer having a first plurality of local bitlines and a second one-hot multiplexer having a second plurality of local bitlines. Each of the first and second pluralities of local bitlines includes is coupled to a memory cell, and includes a passgate arranged on its respective local bitline to allow access to the cell. The first one-hot multiplexer and the second one-hot multiplexer are coupled together such that the highest order local bitline (i.e. corresponding the highest order bit in the group) is coupled to the lowest order bitline of the second one-hot multiplexer, and vice-versa.

Memory structure for providing decreased leakage and bipolar current sensitivity

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Austin, TX, United States of America

Floyd L Dankert