Irvine Sensors Corporation

Dense-pac Microsystems, Inc.

Other

Aprolase Development Co., LLC

Floyd K Eide

Harlan R Isaak

John A Forthun

Layers suitable for stacking in three dimensional, multilayer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are underfilled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Stackable layer containing ball grid array package

Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Stackable layers containing ball grid array packages

A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed with a cavity in which at least one IC chip is placed, electrically connected, and then covered to enclose the chip. Full tests to establish known good quality are performed on individual layers containing enclosed chips. Within each layer horizontal conducting traces connect with conductor-containing vias, in order to carry electrical signals vertically from layer to layer, and also to connect to a ball grid array on the bottom of the stack, the entire surface of which is available for I/O ports.

Stacking layers containing enclosed IC chips

A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed by mechanically and electrically joining an IC-containing TSOP with an external leadframe. Each leadframe contains conductors which are disposed to connect with TSOP leads, transpose signals to other locations on the periphery of the TSOP, and/or connect with other layers in the stack. The TSOP/leadframe layers are stacked and joined, and the leadframe terminals of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.

IC stack utilizing secondary leadframes

A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is fabricated by forming one or more flexible circuit around a TSOP. Each flexible circuit contains conductors which are disposed to connect with TSOP leads, transpose signals to or from various locations on the top or bottom of the TSOP, and/or terminate in ball grid contacts for connection to other layers in the stack. The flexible circuit is bonded to the TSOP such that ball grid contacts are exposed on the top and bottom of the TSOP, and the ball grid array contacts on the bottom of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.

IC stack utilizing BGA contacts

An integrated circuit chip stack includes a stack of chip packages mounted on a substrate. Each chip package includes a plastic packaged chip mounted within a central aperture in a thin, planar frame by soldering leads at opposite ends of the plastic package to conductive pads on an upper surface of the frame adjacent the central aperture. Conductive traces and vias couple the conductive pads to other conductive pads on upper and lower surfaces of the frame adjacent outer edges thereof. The conductive pads adjacent the outer edges are soldered to the conductive pads of adjacent chip packages by dipping the edges of an assembled stack of the chip packages in solder. The chip stack thus formed is mounted on a substrate. Each chip package can be individually addressed by the substrate, such as to enable the chip therein, using a stair step arrangement of the conductive pads in which the pads on the opposite surfaces of each frame are coupled in offset fashion by vias extending through the frame.

Chip stack and method of making same

An IC chip package includes a chip having an upper active surface thereof bonded to the lower surface of a substrate. A plurality of terminals on the active surface are wire bonded within the outer periphery of the chip by bonding wires extending through a plurality of apertures in a lower layer of the substrate to bonding pads on an upper surface of the lower substrate layer. Metallized strips couple the bonding pads to conductive pads at the outer edges of the lower substrate layer. The substrate includes an upper layer having apertures therein. After wire bonding, the apertures in the upper and lower substrate layers are filled with epoxy which is cured and then ground flush with the upper surface of the upper substrate layer. The chip is then lapped to a desired thickness, following which the chip package is electrically tested at various temperatures. The chip package is programmed by wire bonding a chip enable trace to one of a plurality of optional bonding pads of a bonding option array on the lower substrate layer, following which an aperture within the upper substrate layer which provides access to the bonding option array is filled with epoxy which is then cured and ground flat at the upper surface of the substrate. The chip package may then be assembled together with other chip packages into a stack, with the conductive pads of the substrates being joined by strip soldering to form vertical conductive columns.

IC chip package having chip attached to and wire bonded within an

A device for increasing the density of integrated circuit chips on a printed circuit board. A plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board. Each of the input/output data terminals, power and ground terminals of the chips are connected in parallel. Each chip is individually accessed by selectively enabling the desired chip.

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Huntington Beach, CA, United States of America

Floyd K Eide