Texas Instruments Corporation

Floro Lopez Camenforte, Iii

Allan Jerome Daen Rapales

John Paul Quianzon Kwo

Dolores Babaran Milo

James Raymond Maliclic Baello

Armando Tresvalles Clarina, Jr

Joe Anne Feive Carbonell Lopez

A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.

Selective molding for integrated circuit

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Semiconductor devices having metal bumps with flange

A method of registering terminals on an interdigitated chip capacitor ('IDC') with a plurality of contact pads on a substrate. At least one vertically extending nonconductive abutment surface is formed between adjacent ones of the contact pads. A plurality of grooves projecting outwardly from said a central recess is formed on the substrate top portion. At least one sidewall portion of the IDC is urged into abutting engagement with the at least one abutment surface on the substrate. Another method prevent solder from causing short circuits between adjacent terminals. A plurality of grooves extending laterally outwardly from a central recessed portion are formed. The plurality of grooves defining a plurality of inwardly projecting fingers. A plurality of contact pads on are formed on a respective plurality of fingers. A solder bead is formed on at least some of the plurality of contact pads. The at least one solder bead is isolated from adjacent solder beads and adjacent terminals.

Interdigitated chip capacitor assembly

An interdigitated chip capacitor ('IDC') assembly including an IDC having a semiconductor block with a top portion, a bottom portion opposite the top portion, a plurality of sidewall portions extending between the top and bottom portions, and a plurality of terminals located on the sidewall portions; and a substrate having a top portion with a plurality of generally flat, vertically extending, nonconductive abutment surfaces thereon, the sidewall portions of the IDC being abuttingly engaged with at least some of the plurality of abutment surfaces.

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Baguio, Philippines

Floro Lopez Camenforte, Iii