Denso Corporation

Cambridge Enterprise Limited

Infineon Technologies Americas Corp.

Abb Schweiz Ag

Anpec Electronics Corporation

Other

Toyota Jidosha Kabushiki Kaisha

U.S. Philips Corporation

Centre National De La Recherche Scientifique

Fuji Electric Co., Ltd.

Infineon Technologies Austria Ag

University of Electronic Science and Technology of China

Siliconix Incorporated

Hitachi Energy Ltd

Hitachi Energy Switzerland Ag

Florin Udrea

Loizos Efthymiou

Syed Zeeshan Ali

Giorgia Longobardi

Martin Arnold

Andrea De Luca

Gehan A J Amaratunga

Julian Gardner

Gehan Anil Joseph Amaratunga

Gianluca Camuso

Chiu Ng

Rajesh Kumar

Yi Tang

Rajeev Krishna Vytla

Andrei Mihaila

Alice Pei-Shan Hsieh

Ethan Gardner

Nishad Udugampola

Tanya Trajkovic

Chih-Wei Hsu

Vasantha Pathirana

John William Findlay

Mohamed Foysol Chowdhury

Richard Henry Hopper

Yih-Yin Lin

Munaf Rahimo

Yuichi Takeuchi

Mitsuhiro Kataoka

Rajesh Kumar Malhan

Chiara Corvasce

Gehan Anil Amaratunga

Umamaheswara Vemulapati

Thomas Stiasny

Ilie Poenaru

Cerdin Lee

Sheung Wai Fung

Marina Antoniou

C Mark Johnson

Jeremy Rashid

Canhua Li

Cyril Buttay

James Anthony Covington

Suhail Rashid Jeremy

Tatjana Traijkovic

Jonathan Sean Callan

Jonathan Owen Hardie

Neophytos Lophitis

Daniel James Twitchen

Jun Saito

Akitaka Soeno

Christopher John Howard Wort

Wei-Chieh Lin

David Michael Garner

Jan Vobecky

Rainer Minixhofer

Simon Jonathan Stacey

Iulian Nistor

Mohamed Imam

Robert John Miller

Deb Kumar Pal

Luca De-Michielis

Xiaorong Luo

Peter Ward

Nalin L Rupesinghe

Alain Charles

Nicolas Rouger

Howard P Hodson

Julien Pernot

Tim Butler

Alexander Dietrich Hölke

Jeremy Suhail Rashid

Gauthier Chicot

Elizabeth Kho Ching Tee

Steven John Pilkington

Max Shih-kuan Chen

Mihai Brezeanu

Hao-Che Chien

Antonella Tajani

Vasant Ramachandran Kumar

Takao Iwaki

Sohab Sarfraz

David Eon

Etienne Gheeraert

Claudio Falco

Toan Thanh Pham

Shu Yang

Dario Pagnano

Jinming Sun

Ranick Kian Ming Ng

Cerdin Ching Ching Lee

Gianpaolo Romano

Uwe Badstuebner

Philip Neaves

Tara Vishin

David Bruce Vail

Neophythos Lophitis

Lulian Nistor

Richard Henry Hooper

An insulated gate bipolar transistor includes a source electrode, a collector electrode, a source layer, a base layer, a drift layer and a collector layer. Trench gate electrodes extend through the base layer into the drift layer. A channel is located between the source layer, the base layer and the drift layer. A trench Schottky electrode is adjacent to one of the trench gate electrodes and includes an electrically conductive Schottky layer arranged lateral to the base layer and extends through the base layer into the drift layer. The Schottky layer is electrically connected to the source electrode. Collection areas are located in the drift layer at a respective trench gate electrode bottom of the trench gate electrodes or of the trench Schottky electrode. The Schottky layer forms a Schottky contact to the collection area at a contact area.

Insulated gate bipolar transistor including trench Schottky electrode

A III-nitride power semiconductor based heterojunction device comprising a substrate, a first terminal, a second terminal, a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation, and an active heterojunction transistor formed on the substrate. The device further comprises a stand-by signal generation circuit configured to generate a stand-by signal when the input switching signal to the control terminal has not been detected for a set period of time, at least one Miller clamp transistor and driving circuitry associated with the at least one Miller clamp transistor, a voltage regulator circuit configured to provide at least a low power consumption output and a high power consumption output, wherein the low power consumption output is enabled at least during the stand-by mode of operation and the high power consumption output is disabled by the stand-by signal during the stand-by mode of operation, and a rail voltage terminal configured to provide an input to the voltage regulator circuit. The low power consumption output is provided to the driving circuitry of the at least one Miller clamp transistor to thereby maintain the at least one Miller clamp transistor in an on-state during the stand-by mode of operation, and the low power consumption output is provided to the stand-by signal generation circuit to thereby power up the stand-by signal generation circuit.

Stand-by circuit

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

Power semiconductor device with an auxiliary gate structure

We describe a heterojunction based half bridge apparatus formed within a single active area comprising a first heterojunction device and a second heterojunction device, each heterojunction device comprising a drain and a source, each drain comprising a drain contact and each source comprising a source contact; wherein the drain contact of the first heterojunction device and the source contact of the second heterojunction device comprise a common contact. The half bridge apparatus according to the present disclosure may be advantageously more compact and more reliable than existing heterojunction based half bridges.

Heterojunction based half bridge

A power integrated circuit comprising: a heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal, a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device; wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device; wherein the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device and is monolithically integrated within the GaN chip; and wherein the at least one high-side component of the driver is configured to charge up the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN.

Mixed material power devices and driver circuits

An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals. The second Ill-nitride semiconductor region includes a second heterojunction, a third terminal connected to the second Ill-nitride semiconductor region, a fourth terminal laterally spaced from the third terminal and connected to the second Ill-nitride semiconductor region, first highly doped semiconductor regions of a first conductivity type formed over the second Ill-nitride semiconductor region.

III-V semiconductor device with integrated power transistor and start-up circuit

We disclose herein a fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising a semiconductor substrate comprising a first etched portion, a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate, a heating element located within the first dielectric membrane, and a first temperature sensing element spatially separated from the heating element. The fluid sensor further comprises a second temperature sensing element within the dielectric membrane, or the heating element may be further configured to operate as a second temperature sensing element. The separation between the second temperature sensing element and the first temperature sensing element introduces a temperature difference between the second temperature sensing element and the first temperature sensing element, such that a differential signal between the first temperature sensing element and the second temperature sensing element is indicative of the concentration or composition of the fluid based on a thermal conductivity of the fluid.

Thermal fluid sensor

We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor () formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal () operatively connected to the first Ill-nitride semiconductor region; a second terminal () laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal () formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor () formed on a substrate, the second heterojunction transistor comprising: a second Ill-nitride semiconductor region formed over the substrate, wherein the second Ill-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a third terminal operatively connected to the second Ill-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second Ill-nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and a second gate terminal formed over the second Ill-nitride semiconductor region between the third terminal and the fourth terminal and wherein the second heterojunction transistor is used in sensing and protection functions of the first power heterojunction transistor. The device also includes at least one monolithically integrated current sensing transistor () that has a substantially identical structure to the first heterojunction transistor, and wherein the third transistor is scaled to a smaller area or a shorter gate width when compared to the first heterojunction transistor by a scale factor, X, where X is larger than 1. Other embodiments include both internal and external sensing, sensing loads and a feedback circuit to provide overcurrent, gate over-voltage or over-temperature protection.

III-V semiconductor device with integrated protection functions

We disclose herein a sensing device comprising a semiconductor substrate having a first etched portion, a dielectric layer located on or over the semiconductor substrate, wherein the dielectric layer comprises a first dielectric membrane located adjacent to the first etched portion of the semiconductor substrate, a pressure sensing element and/or a flow sensing element within the first dielectric membrane, and a first structure configured to reinforce the dielectric membrane. A first portion of the first structure is located within the first dielectric membrane, the first structure has a higher stiffness than the first dielectric membrane, and the first portion of the first structure is located between a perimeter of the dielectric membrane and the pressure sensing element or flow sensing element.

Flow sensor

A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising: a semiconductor substrate comprising a first etched portion; a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate; a first heating element located within the first dielectric membrane; and a second heating element; wherein the first heating element is arranged to thermally shield the second heating element from ambient temperature changes; wherein the first heating element or the second heating element is configured to operate as a temperature sensing element; wherein the first heating element is configured to operate in a constant temperature or constant resistance mode; wherein the second heating element is configured to operate in a constant current or constant voltage mode or constant power mode; and wherein the sensor is configured to determine a thermal conductivity of the fluid using the temperature sensing element to determine said concentration or composition of the fluid.

We disclose herein a flow sensor comprising: a first substrate comprising an etched portion, a dielectric region located on a first side of the first substrate, wherein the dielectric region comprises at least one dielectric membrane located over the etched portion of the first substrate, a sensing element located on or within the dielectric membrane, and a second substrate adjoining a second side of the first substrate. The first side of the first substrate and the second side of the first substrate are opposite sides. The first substrate and the second substrate cooperate to form a sensing channel through the flow sensor.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor.

An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

III-nitride power semiconductor based heterojunction device

A fluid sensor for sensing a concentration or composition of a fluid, the sensor comprising: a semiconductor substrate comprising a first etched portion and a second etched portion; a dielectric region located on the semiconductor substrate, wherein the dielectric region comprises a first dielectric membrane located over the first etched portion of the semiconductor substrate, and a second dielectric membrane located over the second etched portion of the semiconductor substrate; two temperature sensing elements on or within the first dielectric membrane and two temperature sensing elements on or within the second dielectric membrane; an output circuit configured to measure a differential signal between the two temperature sensing elements of the first dielectric membrane and the two temperature sensing elements of the second dielectric membrane; wherein the first dielectric membrane is exposed to the fluid and the second dielectric membrane is isolated from the fluid.

Thermal fluid sensor with encapsulated fluid region

Growing community of inventors

Cambridge, United Kingdom

Florin Udrea