Infineon Technologies Ag

International Business Machines Corporation

Qimonda Ag

Nanya Technologies Corporation

Florian Schnabel

Stefan Weber

Lawrence Alfred Clevenger

Kenneth Parker Rodbell

Mark Hoinkis

Roy Charles Iggulden

Christian Sichert

Maria Ronay

Chenting Lin

Rolf Weis

Till Schloesser

Ronald G Filippi

Helmut Schneider

Jeremy K Stephens

Ulrike Gruening-von Schwerin

Karl E Boggs

Horatio Seymour Wildman

Sven Schmidbauer

Herbert Palm

Alexander Ruf

Rainer Bartenschlager

Odo Wunnicke

Robert Ploessl

Jens Polney

Hans W Poetzlberger

Wolfgang Henke

Wolfgang Mueller

Wen-Ming Lee

Jin Suk Mun

Jeffery L Hurd

Ebrahim A Mehter

Falk Roewer

Joachim F Nuetzel

A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

Method of producing an integrated circuit having a capacitor with a supporting layer

An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.

Memory with clock-controlled memory access and method of operating the same

A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

Memory component having a novel arrangement of the bit lines

A semiconductor memory device comprises a temperature dependent voltage source for outputting a voltage at its output in dependence on a temperature measured in the semiconductor memory device. At least one memory cell is provided with at least one first transistor. The first transistor includes a first transistor body, which is connected to the output of said temperature dependent voltage source.

Semiconductor memory device

Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.

Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit

A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Device interconnection

A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.

Method of forming a solute-enriched layer in a substrate surface and article formed thereby

A microelectronic structure is formed on a first layer or a substrate. The first layer or substrate is formed with grooves and contact openings. A metal nitride layer of TiN or WN covers the first layer or the substrate at least partially. An alpha-phase tantalum layer is deposited on top of the metal nitride layer. Finally, a metal is deposited to completely fill the grooves and the contact openings.

Method of making a microelectronic structure

The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.

CMP process using indicator areas to determine endpoint

Growing community of inventors

Hoehenkirchen, Germany

Florian Schnabel