Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag

Siemens Aktiengesell Schaft

Infineon Technologies LLC

Florian Schamberger

Robert Kaiser

Helmut Schneider

Thilo Schaffroth

J&uuml;rgen Lindolf

Hans-J&uuml;rgen Krasser

Hermann Ruckerbauer

Michael Bernhard Sommer

Thoai-Thai Le

Andreas Baenisch

Jürgen Lindolf

J&ouml;rg Peter

Jörg Peter

Heinrich Hemmert

An integrated circuit for analyzing the waveform of an input signal includes a first storage circuit and a second storage circuit that are each supplied with the input signal. The first and second storage circuits are controlled by a clock signal. The first storage circuit is used to store a state for the input signal when the clock signal has a rising edge. The second storage circuit is used to store a state for the input signal when the clock signal has a falling edge. An evaluation circuit compares the states of the input signal that are stored in the first and second storage circuits during a selected time span. The comparison can be used to decide whether the input signal assumes periodic fluctuations or an approximately permanently static value during the time span.

Integrated circuit

A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of the connecting elements and the carrier element includes an electrically conductive surface.

Means of mounting for electronic components, arrangement and procedure

A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

Method for testing semiconductor memory modules

Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method can include detecting bit errors using an error identification algorithm. Further, the method can include determining the addresses of faulty memory cells. The method can also include setting a data bit initiating a repair mode in response to detecting a bit error. In the repair mode, a signal present on a data line to the memory chips can be interpreted as a repair command to perform a repair. In addition, the method can include repairing the bit errors by activating redundant memory cells.

Method for repairing hardware faults in memory chips

A comparison method compares the address of a memory cell with a known address of a faulty memory cell in a semiconductor memory module. The module is subdivided into banks and has an address structure in which each address is associated with a bank that is organized in rows and columns and is defined by a row address, a column address and a bank address. Not only the row address is determined, but also the column address and the bank address when a memory access occurs. A bank is activated with a bank selection signal, and the access to a valid address of a faulty memory cell is indicated by an enable register.

Method for comparing the address of a memory access with an already known address of a faulty memory cell

A method for adjusting a resistance in an integrated circuit, the resistance having a first conductive area and a second conductive area between which a dielectric area is arranged, a programming current being conducted through the resistance, the programming current being selected so as to adjust a resistance value of the resistance which is selected from a resistance range and is dependent on the programming current.

Method and circuit for adjusting a resistance in an integrated circuit

An integrated circuit includes a data processing unit, a buffer memory, and a setting memory. The buffer memory performs the function of registers for storing data for the processing unit. The buffer memory is connected to the setting memory. The setting memory can be written to through the buffer memory.

Integrated circuit having a data processing unit and a buffer memory

Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the first interconnect, which end face essentially runs vertically with respect to the substrate, a second interconnect being applied in such a way that it adjoins the dielectric layer with an end face, with the result that an antifuse structure is formed.

Method for producing an antifuse in a substrate and an antifuse structure for integration in a substrate

A circuit configuration for driving a programmable link has a drive circuit for the selection and blowing of the fuse, and also a shift register, by which an activation signal can be fed to the drive circuit. In order to provide the data to be blown, in a preferred embodiment, a volatile memory cell may be provided. The present circuit configuration enables the blowing of fuses and thus repair of defective memory cells in mass memories even after encapsulation of a chip having the mass memory. Moreover, the shift register described effectively prevents impermissibly high currents from being able to occur as a result of simultaneous blowing of too many fuses.

Circuit configuration for driving a programmable link

A circuit configuration is provided for level boosting, in particular for driving a link that can be programmed by an energy pulse, which is also referred to as a fuse. The circuit configuration has a circuit for level boosting and also a logic circuit. The logic circuit combines a first input signal with a second input signal and controls an input of the circuit for level boosting, the output level of an output signal of the circuit for level boosting being greater than the input level. A fusible link can be connected to an output terminal of the circuit for level boosting. Since an input stage of the circuit for level boosting is at the same time a first subcircuit of the logic circuit, the circuit configuration enables an exceptional component and area-saving construction. This has an advantageous effect particularly in mass memory chips.

Circuit configuration for level boosting, in particular for driving a programmable link

A circuit configuration for driving a programmable link has a volatile memory cell, which is coupled to the fuse for the permanent storage of data stored in the volatile memory, and also a shift register, which enables data to be read out from the volatile memory cell and data to be written to the memory cell. In this case, a plurality of shift registers may be interconnected to form a shift register chain for the purpose of driving a plurality of fuses. The shift register chain thus enables fast writing and reading to/from the volatile memory with a low outlay on circuitry.

A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.

Method and apparatus for operating a semiconductor memory at double data transfer rate

The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor component at a connection provided for that purpose on the semiconductor component. The latter has a clock recovery circuit, which obtains a periodic clock signal from the modulated clock signal, and a shift register, to which the modulated clock signal can be fed in a manner clocked by the periodic clock signal and which provides a data signal. The present invention makes it possible, in particular in mass memory chips, to feed in clock signals and also program, address or data signals for the realization of BIST via just one connection contact.

Semiconductor component for connection to a test system

An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Integrated circuit having a programmable element and method of operating the circuit

A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a signal present at the data input, and also a volatile memory, whose output is preferably directly connected to the data input of the drive circuit. A circuit configuration for particularly fast and simple programming of fuses, in particular electrically programmable fuses, is thereby specified.

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Bad Reichenhall, Germany

Florian Schamberger