Intel Corporation

Tahoe Research, Ltd.

Florian Gstrein

Rami Hourani

Manish Chandhok

Eungnak Han

James M Blackwell

Marie Krysak

Robert L Bristol

Richard E Schenker

Scott Bruce Clendenning

Paul Anton Nyhus

Gurpreet Singh

Kevin Lai Lin

Charles Henry Wallace

Patricio E Romero

Grant M Kloster

Valery M Dubin

Szuya S Liao

Jeanette M Roberts

Swaminathan Sivakumar

Ruth Amy Brain

Elliot Tan

Nafees Kabir

David N Shykind

Mark T Bohr

Hui Jae Yoo

Mohit K Haran

Brandon Barnett

James S Clarke

Leonard P Guler

Christopher J Jezewski

David J Michalak

Yan A Borodovsky

Tristan A Tronic

Juan E Dominguez

Tejaswi K Indukuri

Gopinath Bhimarasetti

Stephanie A Bojarski

Tayseer Mahdi

Curtis W Ward

Martin M Mitan

Gordon D Holt

Lauren Doyle

Brandon Jay Holybee

Xuanxuan Chen

Jasmeet S Chawla

Reken Patel

Richard F Vreeland

Nityan Labros Nair

Shane M Harlson

Cen Tan

Rahim Kasim

Kent N Frasure

Giselle Elbaz

Matthew V Metz

Adrien Lavoie

Mauro J Kobrinsky

Elijah V Karpov

Michael Scott Goldstein

Ashish Agrawal

Harsono S Simka

Kanwal Jit Singh

Urusa Alaan

Paul A Zimmerman

Jessica M Torres

Chi-Hwa Tsang

Dan S Lavric

Daniel J Zierath

Todd R Younkin

Ying Pang

Patrick Theofanis

Kiran Chikkadi

Sean Michael Pursel

Lukas M Baumgartel

Michael Robinson

Emily Walker

Jinnie Aloysius

Padmanava Sadhukhan

Joel M Gregie

Gauri Nabar

Thomas Christopher Hoff

Brian Zaccheo

Diane Lancaster

Alan M Meyers

Robert Niffenegger

Robert W Heussner

Ruth A Brain

Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.

Backside wafer treatments to reduce distortions and overlay errors during wafer chucking

Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

Bottom-up fill dielectric materials for semiconductor structure fabrication and their methods of fabrication

Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.

Directed self-assembly enabled subtractive metal patterning

Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

Directed self-assembly enabled patterning over metal layers using assisting features

Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication

Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

Self-assembled guided hole and via patterning over grating

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Advanced lithography and self-assembled devices

Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

Selective metal removal for conductive interconnects in integrated circuitry

Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

Colored gratings in microelectronic structures

Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Contact over active gate structures with metal oxide-caped contacts to inhibit shorting

Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

Contact over active gate structures with metal oxide layers to inhibit shorting

A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

Chemical compositions and methods of patterning microelectronic device structures

Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization having an initiator as the SAM or the SAM attached to another SAM. Other embodiments may be described and/or claimed.

Interconnect structure surface modifications by passivating agents

Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

Directed self-assembly structures and techniques

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Portland, OR, United States of America

Florian Gstrein