Infineon Technologies Ag

Florian Grasse

Wolfgang Bergner

Romain Esteve

Ralf Siemieniec

Dethard Peters

Caspar Leendertz

Rudolf Elpelt

Thomas Aichinger

Bernd Zippelius

Shiqin Niu

Paul Ellinghaus

Jens Peter Konrath

Ravi Keshav Joshi

Stefan Woehlert

Andreas Voerckel

Stefan Krivec

Jochen Hilsenbeck

Stefan Kramp

Hiroshi Narahashi

Richard Gaisberger

Grzegorz Lupina

Hans-Joachim Schulze

Werner Schustereder

Moriz Jelinek

Gregor Langer

Christian Strenger

Kristijan Luka Mletschnig

Axel Sascha Baier

Barbara Englert

Axel König

Bernhard Leitl

A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.

Method of manufacturing a metal silicide layer above a silicon carbide substrate, and semiconductor device comprising a metal silicide layer

A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

Semiconductor device and method for forming a semiconductor device

A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

SiC device with channel regions extending along at least one of the (1-100) plane and the (-1100) plane and methods of manufacturing thereof

A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

SiC device and methods of manufacturing thereof

A silicon carbide body includes a drift structure having a first conductivity type, a body region, and a shielding region. The body and shielding regions, of a second conductivity type, are located between the drift structure and a first surface of the silicon carbide body. First and second trench gate stripes extend into the silicon carbide body. The body region is in contact with a first sidewall of the first trench gate stripe. The shielding region is in contact with a second sidewall of the second trench gate stripe. The second sidewall has a first length in a lateral first direction parallel to the first surface. A supplementary region of the first conductivity type contacts one or more interface areas of the second sidewall. The one or more interface areas have a combined second length along the first direction, the second length being at most 40% of the first length.

Semiconductor device including silicon carbide body and method of manufacturing

According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.

SiC trench transistor device and methods of manufacturing thereof

Growing community of inventors

Hohenthurn, Austria

Florian Grasse