Hrl Laboratories, LLC

Gm Global Technolgoy Operations, Inc.

Florian G Herrault

Melanie Sachiko Yajima

Miroslav Micovic

Shanying Cui

Adam Franklin Gross

Alexandros Margomenos

Xin Ning Guan

Eric M Prophet

Joel C Wong

Tobias A Schaedler

Jonathan James Lynch

Hasan Sharifi

Daniel Yap

Igal Bilik

Christopher Stephen Roper

Keyvan R Sayyah

Zak C Eckel

Oleg M Efimov

Pamela R Patterson

Chia-Ming Chang

David F Brown

Kevin Geary

Dean C Regan

Mark O'Masta

Minh B Nguyen

Robert Mone

Yan Tang

Robert G Nagele

Kayleigh A Porter

Helen Fung

Partia Naghibi

An electronic assembly, having a carrier wafer with a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising first and second integrated circuit contact pads; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; first and second component chips held in said through-wafer cavity each by direct contact of at least a side surface of said first and second component chips with a heat conducting attachment material that fills said through-wafer cavity; said first and second component chips comprising respectively at least a first and a second component contact pads; a barrier having a heat conductivity lower than a heat conductivity of said carrier wafer held by said heat conducting attachment material in said through-wafer cavity between said first and said second component chips.

Thermal isolation between embedded MECA modules

Some variations provide a magnetically anisotropic structure comprising a hexaferrite film disposed on a substrate, wherein the hexaferrite film contains a plurality of discrete and aligned magnetic hexaferrite particles, wherein the hexaferrite film is characterized by an average film thickness from about 1 micron to about 500 microns, and wherein the hexaferrite film contains less than 2 wt % organic matter. The hexaferrite film does not require a binder. Discrete particles are not sintered or annealed together because the maximum processing temperature to fabricate the structure is 500° C. or less, such as 250° C. or less. The magnetic hexaferrite particles may contain barium hexaferrite (BaFeO) and/or strontium hexaferrite (SrFeO). The hexaferrite film may be characterized by a remanence-to-saturation magnetization ratio of at least 0.7. Methods of making and using the magnetically anisotropic structure are also described.

Magnetically anisotropic binder-free films containing discrete hexaferrite nanoplatelets

An interposer for a curved detector. In some embodiments a system includes a curved array photodetector; a first readout integrated circuit, the first readout integrated circuit being substantially flat; and an interposer, between the photodetector and the first readout integrated circuit. The photodetector and the first readout integrated circuit may each have a plurality of electrical contacts. The interposer may include a first conductor connecting a first contact, of the plurality of electrical contacts of the photodetector, and a second contact, of the plurality of electrical contacts of the first readout integrated circuit.

Interposer for curved detector

An electronic assembly, comprising a carrier wafer of a first material, having a top wafer surface and a bottom wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; and an insulator of a second material, different from the first material, having insulator top and bottom surfaces, joined by insulator side surfaces, and having a conducting via that passes through said insulator between said insulator top surface and said insulator bottom surface; wherein the insulator is held in said through-wafer cavity by direct contact of the insulator side surfaces with an attachment metal that fills said through-wafer cavity.

Through-wafer coaxial transition

An array of III-V material transistors singulated from a Si or SiC wafer disposed on a stretchable tape compatible with pick and place tools and a method of forming same.

Singulation process for chiplets

A photonic module and a method of making same, the module having one or more optoelectronic chips, such as a laser diode typically having six sides, with each optoelectronic chip having two opposing sides (a first side and a second side) abutting and electrically connected to metal regions (preferably electro-formed), the two metal regions are physically distinct and electrically separate from each other, the two electro-formed metal regions serving, in use, as heat spreaders for conducting heat away from the optoelectronic chip.

Photonic integrated module with metal embedded chips

A method for creating at least one cavity in a semiconductor substrate including the steps of:

Method for creating cavities in silicon carbide and other semiconductor substrates

An electronic assembly including: a wafer defining at least one cavity; a chip disposed in the cavity; and a metal heat spreader disposed in the cavity, the chip being embedded in the metal heat spreader; wherein the metal heat spreader has at least one elongate microstructure separated from a remainder of the metal heat spreader by at least one channel; wherein the metal heat spreader occupies an area within the cavity that is not occupied by the chip; and wherein the at least one elongate microstructure is configured and arranged in the cavity so as to improve thermal management of the chip by reducing stress across the chip as compared with a configuration and arrangement in which a heat spreader made of the metal and occupying the area within the cavity is a solid without channels. Also, a method for forming the electronic assembly.

Wafer-level integrated micro-structured heat spreaders

An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.

Method and apparatus to increase radar range

An electronic assembly comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising an integrated circuit contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip bottom surface; and a conductor connecting said integrated circuit contact pad and said component contact pad.

Hybrid integrated circuit architecture

Some variations provide a magnetically anisotropic structure comprising a magnetically anisotropic film on a substrate, wherein the magnetically anisotropic film contains a plurality of discrete magnetic hexaferrite particles, wherein the film is characterized by an average film thickness from 1 micron to 5 millimeters, and wherein the magnetically anisotropic film contains from 2 wt % to 75 wt % organic matter. Some variations provide a magnetically anisotropic structure comprising an out-of-plane magnetically anisotropic film on a substrate, wherein the magnetically anisotropic film contains a plurality of discrete magnetic hexaferrite particles, wherein the film is characterized by an average film thickness from 1 micron to 5 millimeters, and wherein the magnetically anisotropic film contains a concentration of hexaferrite particles of at least 40 vol %. The magnetically anisotropic structures are fabricated at low temperatures so that the magnetically anisotropic film may be monolithically integrated into an integrated-circuit fabrication process.

Low-temperature-deposited self-biased magnetic composite films containing discrete hexaferrite platelets

A micro-optical bench includes a substrate having a multi-layer trench and a micro-lens aligned by and mounted to the substrate in the multi-layer trench.

Offset patterned micro-lens and micro-optical bench including the same

Some variations provide a magnetically anisotropic structure comprising a hexaferrite film disposed on a substrate, wherein the hexaferrite film contains a plurality of discrete and aligned magnetic hexaferrite particles, wherein the hexaferrite film is characterized by an average film thickness from about 1 micron to about 500 microns, and wherein the hexaferrite film contains less than 2 wt % organic matter. The hexaferrite film does not require a binder. Discrete particles are not sintered or annealed together because the maximum processing temperature to fabricate the structure is 500&#xb0; C. or less, such as 250&#xb0; C. or less. The magnetic hexaferrite particles may contain barium hexaferrite (BaFeO) and/or strontium hexaferrite (SrFeO). The hexaferrite film may be characterized by a remanence-to-saturation magnetization ratio of at least 0.7. Methods of making and using the magnetically anisotropic structure are also described.

In some variations, the invention provides a method of depositing nanoparticles on a substrate, comprising: providing a substrate having a positive or negative surface charge; optionally depositing a polymer on the substrate, wherein the polymer has opposite charge polarity compared to the substrate; and simultaneously depositing first nanoparticles and second nanoparticles onto the substrate, wherein the first nanoparticles and the second nanoparticles have opposite charge polarities during depositing. Other variations provide a method of depositing a layer of nanoparticles on a substrate, the method comprising: providing a substrate having a positive or negative surface charge; providing faceted nanoparticles; preparing a nanoparticle solution containing the nanoparticles; and adjusting surface charge of the nanoparticles by changing the solution pH to reduce the magnitude of average zeta potential of the nanoparticles, thereby causing aggregation of the nanoparticles onto the substrate surface. Very high packing densities may be achieved with these methods.

Electrostatically driven assembly of nanoparticle materials into dense films

A process for assembling microelectronic or semiconductor chips, comprising: providing a semiconductor chip having an active face with a connection pad; coating the active face of the semiconductor chip with a conformal dielectric material layer, such that the connection pad is completely coated by the conformal dielectric material layer; temporarily adhering the active face of the semiconductor chip to a carrier wafer; temporarily adhering the carrier wafer to a wafer-with-a-through-cavity such that the semiconductor chip extends into the through-cavity; assembling the semiconductor chip to the wafer-with-the-through-cavity by filling the through-cavity with a heat spreader material; releasing the assembled semiconductor chip and wafer-with-the-through-cavity from the carrier wafer; removing the conformal dielectric material layer from at least a portion of the connection pad; and forming an electrical connection to said at least a portion of the connection pad.

Growing community of inventors

Agoura Hills, CA, United States of America

Florian G Herrault